Sying-Jyan Wang

National Chung Hsing University — Taiwan

Engineering · Physical Sciences

20h-index1.4kcitations131works5.02yr avg
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Research Topics

Integrated Circuits and Semiconductor Failure Analysis(62), VLSI and Analog Circuit Testing(59), Low-power high-performance VLSI design(20), Industrial Vision Systems and Defect Detection(19), Embedded Systems Design Techniques(16)

Publications131 total

Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips
ACM Transactions on Design Automation of Electronic Systems·2024· 4 citedOpen Access
Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2024· 6 cited
Implementing OIML R46 Communication Unit for DLMS/COSEM Security Suite 1 and Passing CTT V3.1 Test
2023· 1 cited
Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
2023· 1 cited
Automatic Power Trace Alignment for Side-Channel Analysis
Research Square (Research Square)·2023Open Access
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults
Integration·2022· 5 cited
Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication
2022
Automatic Alignment for Side-Channel Attack Against Cryptographic Modules
2022 IET International Conference on Engineering Technologies and Applications (IET-ICETA)·2022· 2 cited
Zero Payload Enhanced AES Cryptography Against Side-Channel Attacks
2022 IET International Conference on Engineering Technologies and Applications (IET-ICETA)·2022· 2 cited
Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
2022· 3 cited
Wafer Defect Pattern Classification with Explainable-Decision Tree Technique
2022· 7 cited
Trojan Insertions of Fully Programmable Valve Arrays
2022· 4 cited
Improving IJTAG Test Efficiency and Security
2022· 2 cited
Wafer Defect Pattern Labeling and Recognition Using Semi-Supervised Learning
IEEE Transactions on Semiconductor Manufacturing·2022· 24 cited
Wafer Scratch Pattern Reconstruction for High Diagnosis Accuracy and Yield Optimization
IEEE Transactions on Semiconductor Manufacturing·2022· 8 cited
TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
IEEE Transactions on Semiconductor Manufacturing·2022· 8 cited
Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)·2022· 4 cited
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
2021· 5 cited
WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
2021· 3 cited
Integrated Scratch Marker for Wafer Defect Diagnosis
2021
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Frequent Co-authors

Katherine Shu-Min Li(22), Andrew Yi-Ann Huang(9), Ken Chau-Cheung Cheng(8), Leon Li-Yang Chen(8), Leon Chou(7), Chen-Shiun Lee(7), Nova Cheng-Yen Tsai(6), Peter Yi-Yu Liao(6), Hsing-Chung Liang(5), Niraj K. Jha(4), Jwu E. Chen(4), Tsung-Yi Ho(4), Tsi-Ming Tsai(3), Nan-Cheng Lai(3), Jain-De Li(3), Chang Kyu Byun(2), Meiping Zhao(2), Jiwei Li(2), Chun‐Lung Hsu(2), Xuhao Jiang(2)