Javier A. Salcedo

Engineering · Physical Sciences

18h-index827citations88works0.02yr avg
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Research Topics

Electrostatic Discharge in Electronics(71), Electromagnetic Compatibility and Noise Suppression(42), Integrated Circuits and Semiconductor Failure Analysis(35), Semiconductor materials and devices(32), Advancements in Semiconductor Devices and Circuit Design(21)

Publications88 total

S3904 A Rare Case of Histiocytic Sarcoma Presenting in the Terminal Ileum
The American Journal of Gastroenterology·2025
Device for Protecting High Frequency and High Data Rate Interface Applications in FinFET Process Technologies
2022· 3 cited
Balancing the Trade-off Between Performance and Mis-trigger Immunity in Active Feedback-based High-voltage Tolerant Power Clamps
2020· 2 cited
A New Low-Capacitance High-Voltage-Tolerant Protection Clamp for High-Speed Applications
IEEE Transactions on Electron Devices·2020· 8 cited
Stacking Switch to Achieve Low-Trigger and High-Holding-Voltage-Clamp Characteristics
IEEE Transactions on Electron Devices·2020· 9 cited
Integrating Solid State Protection with a RF-MEMS Switch for Achieving ESD Robustness
2019
Characterization and Modeling of the Transient Safe Operating Area in LDMOS Transistors
2019· 5 cited
Modeling and Simulation of Comprehensive Diode Behavior Under Electrostatic Discharge Stresses
IEEE Transactions on Device and Materials Reliability·2018· 27 cited
Compact and Fast-Response Voltage Clamp for Bi-Directional Signal Swing Interface Applications
IEEE Electron Device Letters·2018· 32 cited
Distributed ESD Protection Network for Millimetre-Wave RF Applications
2018· 3 cited
Thermal failure and voltage overshoot models for diode behavior under electrostatic discharge stresses
2018· 1 cited
ESD Protection in Automotive Integrated Circuit Applications
2017
High blocking voltage ESD timer clamp with mis-trigger protection
2017
Heterogeneous stacking silicon controlled rectifier design with improved ESD performance
2017· 1 cited
Embedded shunt diode pair to suppress overshoot voltage
2017· 5 cited
ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications
Microelectronics Reliability·2017· 13 cited
A New Method to Estimate Failure Temperatures of Semiconductor Devices Under Electrostatic Discharge Stresses
IEEE Electron Device Letters·2016· 18 cited
Design of ESD protection for fault tolerant interface applications with EMC immunity
2016
Investigation of forward transient characteristics of vertical GaN-on-GaN p-n diodes
2016· 1 cited
Novel structure embedded with dual-diodes and silicon controlled rectifier for high speed I/O applications
2016
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Frequent Co-authors

Jean-Jacques Hajjar(34), Juin J. Liou(25), Yuanzhong Zhou(17), Srivatsan Parthasarathy(13), Slavica Malobabic(8), Kalpathy B. Sundaram(6), Linfeng He(5), A. Ortíz-Conde(4), Alan Righter(4), Meng Miao(4), David F. Ellis(4), Aihua Dong(4), Qiang Cui(3), Francisco J. García-Sánchez(3), Y. Yue(3), Hang Li(3), Sirui Luo(3), J.J. Hajjar(2), Zhiwei Liu(2), J.J. Liou(2)