B. M. Prabhu Prasad

Indian Institute of Information Technology Allahabad — India

Computer Science · Physical Sciences

4h-index56citations19works1.42yr avg
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Research Topics

Interconnection Networks and Systems(10), Parallel Computing and Optimization Techniques(9), Embedded Systems Design Techniques(6), Supercapacitor Materials and Fabrication(2), Robotic Path Planning Algorithms(2)

Publications19 total

Exploring Emerging Materials and Architectures for Energy-Efficient and High-Performance Computing
2025
Historic Facial Image Restoration Using SRGAN
2025
Energy-Efficient Depthwise Separable CNNs for Classification and Segmentation of Lung Cancer Nodules
2025
Enhancing Data Management in Industry 5.0: The Role of Digital Twins in Optimizing Industrial Operations
2025· 2 cited
Implementation and Comparison of Path Planning Algorithms for Autonomous Navigation
2024· 1 cited
Object Detection and Classification Framework for Analysis of Video Data Acquired from Indian Roads
Sensors·2024· 4 citedOpen Access
Innovative Healthcare Metaverse, Explainable AI, and Blockchain Paradigm Shift
Advances in medical technologies and clinical practice book series·2024· 3 cited
Pilot DroneUI: An User Interface to Control UAV using Robot Operating System
2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)·2022· 2 cited
Real-time Human Motion Tracking and Reconstruction using IMU Sensors
2022 International Conference on Electrical, Computer and Energy Technologies (ICECET)·2022· 7 cited
Hy-BTree: An efficient Tree based topology for FPGA based NoC implementation
2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)·2021· 1 cited
FPGA friendly NoC simulation acceleration framework employing the hard blocks
Computing·2021· 7 cited
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA
Wireless Personal Communications·2020· 3 cited
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks
Circuits Systems and Signal Processing·2020· 9 cited
Analysis of cache behaviour and software optimizations for faster on-chip network simulations
International Journal of Systems Assurance Engineering and Management·2019
High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks
2019· 4 cited
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA
2019· 6 cited
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs
Journal of Circuits Systems and Computers·2018· 3 cited
Cache analysis and software optimizations for faster on-chip network simulations
2016
Two level cache architectures
2003· 4 cited

Frequent Co-authors

Khyamling Parane(9), Basavaraj Talawar(9), Bidyapati Kumar(3), Manjunath K Vanahalli(3), Pavan Kumar B N(3), Vivaan Sharma(2), G. N. Girish(2), B.K. Chethana(2), Ratnesh Kherudkar(2), Bharatesh Chakravarthi(1), B Chethana(1), Mani Azimi(1), Krishnaraj Bhat(1), Aayushi Padia(1), T. N. Aryan(1), Sharan Thummagunti(1), Yong-Guk Kim(1), Raju Imandi(1), Yong Guk Kim(1), Raju Imandi(1)