Chetan Vudadha

Birla Institute of Technology and Science - Hyderabad Campus — India

Engineering · Physical Sciences

12h-index444citations36works1.72yr avg
OpenAlex↗ORCID↗Google Scholar↗Lab page↗

Accepting Students?

No reports yet. Know if this professor is taking students?

Research Topics

Low-power high-performance VLSI design(21), Advancements in Semiconductor Devices and Circuit Design(18), Analog and Mixed-Signal Circuit Design(15), Quantum-Dot Cellular Automata(12), Quantum Computing Algorithms and Architecture(7)

Publications36 total

Accuracy Reconfigurable Carry Bypass Approximate Adder as Co-processor to RISC-V
Lecture notes in electrical engineering·2024
Design of a Ternary Logic Processor Using CNTFET Technology
Circuits Systems and Signal Processing·2024· 2 cited
Design of CNFET-based Ternary Conditional Sum Adders using Binary Carry Propagation
2024· 3 cited
PDCCH Signaling Constrained Mean SNR-Based Resource Allocation for Semi-Persistent Scheduler
2023
Low Power and High Speed Comparator Design in Quantum-dot Cellular Automata
2023· 1 cited
Power efficient designs of CNTFET-based ternary SRAM
Microelectronics Journal·2023· 10 cited
Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation
Journal of Circuits Systems and Computers·2023· 1 cited
An Approximate Full-Adder to Eliminate Carry Propagation in Lower Significant Stage of a Multi-Digit Adder
2023· 3 cited
Evaluation of x86 and ARM architectures using compute-intensive workloads
2022 IEEE International Symposium on Smart Electronic Systems (iSES)·2022· 5 cited
Design of CNTFET-based Ternary Logic circuits using Low power Encoder
2022 IEEE International Symposium on Smart Electronic Systems (iSES)·2022· 5 cited
Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits
IEEE Transactions on Nanotechnology·2022· 18 cited
Optimization of Reversible Circuits Using Gate Pair Classification
SN Computer Science·2021· 1 cited
Design of CNFET-based Low-Power Ternary Sequential Logic circuits
2021· 6 cited
FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design
2020· 1 cited
Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach
IEEE Transactions on Nanotechnology·2020· 53 cited
A Novel Low Power Ternary Multiplier Design using CNFETs
2020· 18 cited
Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs
2019· 10 cited
Design of Ternary Logic Circuits Using CNFETs
2018· 2 cited
Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers
IEEE Transactions on Circuits and Systems I Regular Papers·2018· 75 cited
Design Methodologies for Ternary Logic Circuits
2018· 34 cited
page 1 of 2Next →

Frequent Co-authors

P. Sai Phaneendra(11), M.B. Srinivas(8), M. B. Srinivas(8), Sharvani Gadgil(7), V. Sreehari(7), N. Moorthy Muthukrishnan(5), Syed Ershad Ahmed(4), Sreehari Veeramachaneni(3), Sai Phaneendra Parlapalli(3), Goutham Makkena(2), Goli Naga Sandesh(2), Prashant Wali(2), Gopal Krishna Kamath(2), A. Surya(1), Saurabh Agrawal(1), M. D. Srinivas(1), Srinivas M.B.(1), Rajagopalan Srinivasan(1), Aditya Dusi(1), M. Venkata Swamy Nayudu(1)