C. Diorio

University of Washington — United States

Engineering · Physical Sciences

26h-index2.8kcitations73works0.02yr avg
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Research Topics

Advanced Memory and Neural Computing(32), Analog and Mixed-Signal Circuit Design(29), Advancements in Semiconductor Devices and Circuit Design(24), Semiconductor materials and devices(20), CCD and CMOS Imaging Sensors(15)

Publications73 total

A micro-power neural spike detector and feature extractor in .13μm CMOS
2008· 34 cited
A 3 $\mu$W CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation
IEEE Journal of Solid-State Circuits·2008· 61 cited
A Compact Pulse-Based Charge Pump in 0.13 μm CMOS
2007· 5 cited
Floating-Gate MOS Synapse Transistors
2007· 20 cited
Introduction: From Neurobiology to Silicon
2007
Self-tuning adaptive delay sequential elements
Microelectronics Journal·2007
Design and Application of Adaptive Delay Sequential Elements
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2006· 2 cited
A 2.92μW Hardware Random Number Generator
2006· 31 cited
A Random Projection Imager for Visual Pattern Classification in Analog VLSI
2006· 1 cited
Miniature animal computer interfaces: applied to studies of insect flight and primate motor pathways
2006
A2 .92µW Hardware Random Number Generator
2006· 1 cited
A reconfigurable VLSI learning array
2005· 6 cited
An autonomous implantable computer for neural recording and stimulation in unrestrained primates
Journal of Neuroscience Methods·2005· 124 cited
A miniature implantable computer for functional electrical stimulation and recording of neuromuscular activity
2005· 14 cited
Measurement of ultralow gate tunneling currents using floating-gate integrator technique
IEEE Electron Device Letters·2005· 11 cited
Study of stress-induced leakage current and charge loss of nonvolatile memory i cell with 70Å tunnel oxide using floating-gate integrator technique
2005· 1 cited
In-Circuit Self-Tuning of Clock Latencies
2005
Adaptive signal processing and correlational learning in mixed-signal vlsi
2005· 3 cited
On-Chip Compensation of Device-Mismatch Effects in Analog VLSI Neural Networks
2004· 14 cited
Reliability of pFET EEPROM With 70-Å Tunnel Oxide Manufactured in Generic Logic CMOS Processes
IEEE Transactions on Device and Materials Reliability·2004· 37 cited
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Frequent Co-authors

P. Hasler(23), B.A. Minch(22), Carver Mead(12), Miguel Figueroa(11), Seth Bridges(6), T. Humes(5), Daniel Hsu(4), David Hsu(4), A. Pesavento(3), J. Mavoori(3), John Hyde(3), Jeremy Holleman(3), Brian Otis(3), Marc Thomas(2), Jeff Bilmes(2), Ron Paulsen(2), A. Minch(1), R. Glidden(1), C. Bockorick(1), Sharp Cooper(1)