Luca Amarù

Synopsys (United States) — United States

Engineering · Physical Sciences

25h-index2.5kcitations113works0.62yr avg
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Research Topics

Low-power high-performance VLSI design(38), Formal Methods in Verification(28), Advancements in Semiconductor Devices and Circuit Design(28), VLSI and Analog Circuit Testing(27), Semiconductor materials and devices(25)

Publications113 total

ML-Inspired Logic Synthesis: Improving Multiplier Circuits
2025
Scalable Sequential Logic Synthesis Using Observability Don’t Care Conditions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2025Open Access
A MAJestic Synthesis Review [Special Section on 2025 IEEE Kirchhoff Award]
IEEE Circuits and Systems Magazine·2025
Three-Independent-Gate Transistors: The Swiss Army Knife of Devices [Special Section on 2025 IEEE Kirchhoff Award]
IEEE Circuits and Systems Magazine·2025· 1 cited
Scalable Sequential Optimization Under Observability Don't Cares
2024· 2 cited
Scalable Sequential Optimization Under Observability Don't Cares
arXiv (Cornell University)·2023Open Access
An RTL-to-GDSII Flow for Single Flux Quantum Circuits Based on an Industrial EDA Toolchain
IEEE Transactions on Applied Superconductivity·2023· 8 cited
Improving LUT-based optimization for ASICs
Proceedings of the 59th ACM/IEEE Design Automation Conference·2022· 6 citedOpen Access
Majority-based Design Flow for AQFP Superconducting Family
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)·2022· 12 citedOpen Access
LUT-Based Optimization For ASIC Design Flow
2021· 9 citedOpen Access
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping
2021· 30 cited
Deep Integration of Circuit Simulator and SAT Solver
2021· 16 cited
Read your Circuit
2021· 19 citedOpen Access
SAT-Sweeping Enhanced for Logic Synthesis
2020· 15 citedOpen Access
A Scalable Mixed Synthesis Framework for Heterogeneous Networks
2020· 5 cited
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks
2020· 26 citedOpen Access
Extending Boolean Methods for Scalable Logic Synthesis
IEEE Access·2020· 5 citedOpen Access
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.
IACR Cryptology ePrint Archive·2020
LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper
2019· 46 cited
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs
2019· 1 cited
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Frequent Co-authors

Giovanni De Micheli(41), Pierre‐Emmanuel Gaillardon(33), Mathias Soeken(15), Eleonora Testa(9), Odysseas Zografos(6), Alan Mishchenko(6), Anupam Chattopadhyay(5), Robert K. Brayton(4), Patrick Vuillod(4), Jiong Luo(4), Winston Haaswijk(3), Rudy Lauwereins(3), Praveen Raghavan(3), Walter Lau Neto(3), Heinz Riener(3), Janet Olson(3), Anne Siemon(2), Eike Linn(2), Rainer Waser(2), Bart Sorée(2)