Sahand Salamat

University of California, San Diego — United States

Engineering · Physical Sciences

12h-index653citations23works0.02yr avg
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Research Topics

Ferroelectric and Negative Capacitance Devices(12), Advanced Memory and Neural Computing(11), Low-power high-performance VLSI design(6), Parallel Computing and Optimization Techniques(5), VLSI and FPGA Design Techniques(4)

Publications23 total

HD2FPGA: Automated Framework for Accelerating Hyperdimensional Computing on FPGAs
2023· 12 cited
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD
ACM Transactions on Reconfigurable Technology and Systems·2022· 24 cited
Store-n-Learn: Classification and Clustering with Hyperdimensional Computing across Flash Hierarchy
ACM Transactions on Embedded Computing Systems·2022· 5 citedOpen Access
NASCENT: Near-Storage Acceleration of Database Sort on SmartSSD
2021· 43 citedOpen Access
Revisiting HyperDimensional Learning for FPGA and Low-Power Architectures
2021· 84 cited
FPGA Acceleration of Protein Back-Translation and Alignment
2021· 1 cited
HyperRec
2021· 13 citedOpen Access
Residue-Net
2021· 6 citedOpen Access
Revisiting FPGA Routing under Varying Operating Conditions
2020· 2 cited
SHEAR <i>er</i>
2020· 12 citedOpen Access
SHEARer: Highly-Efficient Hyperdimensional Computing by Software-Hardware Enabled Multifold Approximation
arXiv (Cornell University)·2020· 2 citedOpen Access
Accelerating Hyperdimensional Computing on FPGAs by Exploiting Computational Reuse
IEEE Transactions on Computers·2020· 51 cited
FPGA Acceleration of Sequence Alignment: A Survey
arXiv (Cornell University)·2020· 15 citedOpen Access
QuantHD: A Quantization Framework for Hyperdimensional Computing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2019· 96 cited
FPGA Energy Efficiency by Leveraging Thermal Margin
2019· 3 citedOpen Access
Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms
2019· 9 citedOpen Access
SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing
2019· 59 cited
F5-HD
2019· 83 citedOpen Access
FACH
2019· 46 citedOpen Access
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2018· 9 cited
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Frequent Co-authors

Mohsen Imani(12), Behnam Khaleghi(11), Tajana Rosing(10), Tajana Rosing(10), Yeseong Kim(5), Saransh Gupta(3), Jaeyoung Kang(3), Justin Morris(3), Barış Akşanlı(3), Bijan Alizadeh(3), Samuel Bosch(2), Yang Seok Ki(2), Anthony Thomas(2), Fatemeh Asgarinejad(2), Mehrnaz Ahmadi(2), Sohum Datta(1), Sharadhi Ramakrishna(1), Jan M. Rabaey(1), Zhuowen Zou(1), Sanjay Anantha Rao(1)