R. Seshasayanan

Meenakshi Academy of Higher Education and Research — India

Engineering · Physical Sciences

13h-index345citations62works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(15), Advanced Wireless Communication Techniques(12), Image and Signal Denoising Methods(11), Wireless Communication Networks Research(10), Digital Filter Design and Implementation(10)

Publications62 total

High performance fir filter based on vedic mathematics
International Journal of Systems Assurance Engineering and Management·2023· 12 cited
An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec
Transactions of the Institute of Measurement and Control·2021· 2 cited
HIGH PERFORMANCE PID CONTROLLER FOR PRESSURE PROCESS STATION
Journal of Emerging Technologies and Innovative Research·2020· 1 cited
Development of Combinational Circuits by Encoding on the Basis of Developmental Biology
Computational Intelligence and Neuroscience·2020Open Access
Medical image DENOISING scheme using discrete wavelet transform and optimization with different noises
Concurrency and Computation Practice and Experience·2019· 7 cited
Low power single precision BCD floating–point Vedic multiplier
Microprocessors and Microsystems·2019· 15 cited
Performance Improvement of Antilogarithmic Converter Using 28 Regions Error Correction Scheme
Asian Journal of Computer Science and Technology·2019Open Access
Medical image denoising by using discrete wavelet transform: Neutrosophic theory new direction
Zenodo (CERN European Organization for Nuclear Research)·2019· 1 citedOpen Access
WITHDRAWN: Medical image denoising by using discrete wavelet transform: Neutrosophic theory new direction
Cognitive Systems Research·2018· 10 cited
Denoising Brain Images with the Aid of Discrete Wavelet Transform and Monarch Butterfly Optimization with Different Noises
Journal of Medical Systems·2018· 15 cited
A Survey of Algorithmic and Architectural Modifications for Enhancing the Performance of Booth Multipliers
2018
Optimization of logarithmic converter for LNS based SOC
Cluster Computing·2018
A COMPARATIVE STUDY OF ADDER ARCHITECTURES FOR 3X MULTIPLE GENERATION IN RADIX-8 BOOTH ENCODING
2018
Observed Variability of Surface Layer in the Central Bay of Bengal:Results of Measurements Using Glider
Current Science·2017· 3 cited
Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding
Cluster Computing·2017· 4 cited
A precise positioning conditional probability estimator for fixed width booth multipliers
2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI)·2017· 1 cited
Satellite Image Resolution Enhancement Using Evolved Wavelet Filters
Journal of Computational and Theoretical Nanoscience·2017· 2 cited
Optimized Double Domino Manchester Carry Chain Adders in 45 nm Technology
Journal of Computational and Theoretical Nanoscience·2016
Impulse Noise Removal Using Adaptive Bilateral Filter with Robust Noise Detector
Journal of Computational and Theoretical Nanoscience·2016· 3 cited
FPGA implemented testbed in 8-by-8 and 2-by-2 OFDM–MIMO channel estimation and design of baseband transceiver
SpringerPlus·2016· 9 citedOpen Access
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Frequent Co-authors

Dhandapani Vaithiyanathan(10), K.S. Vishvaksenan(9), K. Kunaraj(5), T.E. Aravindan(4), Shijo Zacharia(3), Tata Sudhakar(3), M. A. Atmanand(3), S.V. Priya(3), V. Vijayakumar(3), S. Anith(2), J. Nargis(2), Yuvaraj Krishnamoorthy(2), S. Ramesh(2), R. R. Rao(2), K. Senthilkumar(1), Sudharssun Subramanian(1), J. Keerthiga(1), V. Ramya(1), S. K. Mahendran(1), N. Mohana Priya(1)