Carl Sechen

The University of Texas at Dallas — United States

Engineering · Physical Sciences

32h-index3.7kcitations166works0.32yr avg
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Research Topics

VLSI and FPGA Design Techniques(87), Low-power high-performance VLSI design(80), VLSI and Analog Circuit Testing(71), Embedded Systems Design Techniques(21), Interconnection Networks and Systems(20)

Publications166 total

An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
2025
A TRAP for SAT: On the Imperviousness of a Transistor-Level Programmable Fabric to Satisfiability-Based Attacks
IACR Transactions on Cryptographic Hardware and Embedded Systems·2025· 1 citedOpen Access
Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2024
Testing a Transistor-Level Programmable Fabric: Challenges and Solutions
2024
Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric
2023· 2 cited
MTBoM: Metal Trace to Bill of Materials Generation for PCB Reverse Engineering
2022· 3 cited
Essential Standard Cell Library Composition
2022· 5 cited
Toward Accurate Timing Analysis for Transistor-Level Programmable Fabrics
2022· 3 cited
Optimal Standard Cell Library Composition for 7nm
2020· 3 cited
CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric
2020· 1 cited
ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric
2020· 5 cited
An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs
2020· 4 cited
Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage
2019
Toward an Open-Source Digital Flow
2019· 146 citedOpen Access
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA
2019· 33 citedOpen Access
Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming
2019· 34 cited
On designing optimal camouflaged layouts
2017· 1 cited
Are standalone gate size and V<inf>T</inf> optimization tools useful?
2017· 2 cited
A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration
2017· 12 cited
Improved lagrangian relaxation-based gate size and V<sub>T</sub> assignment for very large circuits
2017· 3 cited
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Frequent Co-authors

Gin Yee(7), W. H. Swartz(5), Alberto Sangiovanni‐Vincentelli(4), Hiran Tennakoon(4), T. Thorp(4), Hsiao-Ping Tseng(3), Ted Stanion(3), Wern-Jieh Sun(2), Qicheng Yu(2), Meisam Heidarpour Roshan(2), Samira Zaliasl(2), Kimo Joo(2), Kamran Souri(2), Rajkumar Palwai(2), Sudhakar Pamarti(2), Nicholas J. Miller(2), Joseph C. Doll(2), Carl Arft(2), S. Tabatabaei(2), Aaron Partridge(2)