Razieh Ghasemi

Iran University of Science and Technology — IR

Engineering · Physical Sciences

7h-index158citations23works3.02yr avg
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Research Topics

Analog and Mixed-Signal Circuit Design(10), Advancements in PLL and VCO Technologies(6), Radio Frequency Integrated Circuit Design(5), Advancements in Semiconductor Devices and Circuit Design(5), CCD and CMOS Imaging Sensors(4)

Publications23 total

Implementation of two new 10-bit 1 GS/s hybrid DACs with a novel gain error calibration technique
Integration·2025
An X-band high linearity rail-to-rail variable-gain LNA in 65 nm CMOS technology
Analog Integrated Circuits and Signal Processing·2025
A Low-Power 10-Bit 2GS/s Hybrid Time-Interleaved Digital-to-Analog Converter with a New Neutrolized-Glitch Unit Current Cell in 65 nm CMOS Technology
Circuits Systems and Signal Processing·2024· 2 cited
Electrospun synthesis of polyaniline and titanium dioxide nanofibers as potential electrode materials in electrochemical hydrogen storage
Renewable Energy·2024· 10 citedOpen Access
A low phase noise quadrature VCO using super‐harmonic coupling technique in 65‐nm CMOS technology
International Journal of Circuit Theory and Applications·2023· 1 cited
Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits
Frontiers of Information Technology & Electronic Engineering·2023· 3 cited
A Low Noise Figure Rail-to-Rail Variable-Gain LNA for 900-MHz LoRa Application in 65nm CMOS Technology
2022· 1 citedOpen Access
High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures
IEEE Embedded Systems Letters·2022· 26 cited
Fabrication and Optimization of Electrospun Polymeric NanofibersLoaded with 5-Fluorouracil and Rosemary Extract
Pharmaceutical Nanotechnology·2022· 4 cited
A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology
International Journal of Circuit Theory and Applications·2021· 3 cited
Design and Analysis of a Low-Power Two-Stage Dynamic Comparator with 40ps Delay in 65nm CMOS Technology
2021· 3 cited
A low-power high-speed two-stage dynamic comparator with a new offset cancellation technique in 90 nm CMOS technology
2020· 8 cited
A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology
Microelectronics Journal·2019· 26 cited
A novel 6GHz/ 573µwatt/ 30ps Dynamic Comparator with complementary differential input in 65nm CMOS Technology
2019· 4 cited
A Novel 10-bit 1.2GS/s Hybrid Digital to Analog Converter with 8.4mW Power Consumption
2019· 1 cited
A general micromechanical model to predict elastic and strength properties of balanced plain weave fabric composites
Journal of Composite Materials·2017· 11 cited
The Effect of Electrolytic Capacitors on SMPS’s Failure Rate
International Journal of Machine Learning and Computing·2013· 6 citedOpen Access
EMB Charger and MPPT Merging in Micro-Satellites
International Journal of Machine Learning and Computing·2013· 2 citedOpen Access
Energy Storage Selection for LEO Satellites
International Journal of Machine Learning and Computing·2013· 12 citedOpen Access
Reliability of MPPT Converter in Different Operating Modes
International Journal of Machine Learning and Computing·2013· 6 citedOpen Access
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Frequent Co-authors

Hossein Ghasemian(6), B. Abdi(5), Sayyed Mohammad Mehdi Mirtalaei(5), Mohammad Azim Karami(5), Ebrahim Abiri(4), Mohammad Reza Salehi(3), Ayoub Sadeghi(2), Nabiollah Shiri(2), Amirhossein Ahmadi(2), Hassan Daryanavard(2), R. Mozafari-Dana(1), Seyed Mohammad Etrati(1), Saeed Shaikhzadeh Najar(1), A. Alimardani(1), M.M. Shokrieh(1), Reza Mosalmani(1), Ali Mohammadi-Ganjgah(1), Maryam Shaterian(1), Hamed Bahrami(1), Reza Rasuli(1)