Man Shi

KU Leuven — Belgium

Computer Science · Physical Sciences

8h-index332citations21works5.62yr avg
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Research Topics

Advanced Neural Network Applications(8), Advanced Memory and Neural Computing(8), CCD and CMOS Imaging Sensors(5), Ferroelectric and Negative Capacitance Devices(3), Parallel Computing and Optimization Techniques(2)

Publications21 total

Diffuse Laser Cooling Based on the $6\mathrm{P}_{3/2}$ Excited State of Rubidium Atoms via 420 nm Blue Light
arXiv (Cornell University)·2025Open Access
A 16NM 550-1320 BTOPS/W NPU Exploiting Training-Free Structured Bit-Level Sparsity and Dynamic Dataflow Processing
2025
Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format
2025· 4 cited
Sparsity-Aware Hardware: From Overheads to Performance Benefits
IEEE Solid-State Circuits Magazine·2025
SparseCol: A 1320 BTOPS/W Precision-Scalable NPU Exploiting Training-Free Structured Bit-Level Sparsity and Dynamic Dataflow
IEEE Journal of Solid-State Circuits·2025
Leveraging Deep Spatiotemporal Sequence Prediction Network with Self-Attention for Ground-Based Cloud Dynamics Forecasting
Remote Sensing·2024· 3 citedOpen Access
Complementary Oxide Semiconductor-Based 2T0C DRAM Macro with CFET Peripherals Using TeO<sub>x</sub>-PFET/IGZO-NFET for 3D Memory Integration
2024· 8 cited
Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format
arXiv (Cornell University)·2024Open Access
Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware Accelerators
2024· 7 cited
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration
2024· 34 citedOpen Access
COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2023· 6 citedOpen Access
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories
2023· 4 citedOpen Access
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge
IEEE Journal of Solid-State Circuits·2022· 56 cited
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC
2022 IEEE International Solid- State Circuits Conference (ISSCC)·2022· 77 cited
ML Processors Are Going Multi-Core: A performance dream or a scheduling nightmare?
IEEE Solid-State Circuits Magazine·2022· 14 cited
Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing
IEEE Journal on Emerging and Selected Topics in Circuits and Systems·2021· 11 cited
Erratum to “Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning” [Feb 21 658-673]
IEEE Journal of Solid-State Circuits·2021Open Access
Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning
IEEE Journal of Solid-State Circuits·2020· 52 cited
STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction
2020· 23 cited
A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression
IEEE Transactions on Circuits & Systems II Express Briefs·2019· 33 cited
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Frequent Co-authors

Marian Verhelst(13), Vikram Jain(5), Chao Fang(5), Leibo Liu(4), Shaojun Wei(4), Shouyi Yin(4), Antony Joseph(4), Pouya Houshmand(3), Fengbin Tu(3), Feng Xiong(3), Robin Geens(3), Arne Symons(3), Wim Dehaene(3), Kodai Ueyoshi(2), Ioannis A. Papistas(2), Giuseppe Maria Sarda(2), Qilin Zheng(2), Debjyoti Bhattacharjee(2), Arindam Mallik(2), Peter Debacker(2)