Alexandru Amaricăi

Engineering · Physical Sciences

10h-index363citations78works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(26), Error Correcting Code Techniques(22), Advanced Wireless Communication Techniques(20), Numerical Methods and Algorithms(18), Radiation Effects in Electronics(14)

Publications78 total

Iterative Gradient Descent Decoding for Real Number LDPC Codes
arXiv (Cornell University)·2024Open Access
Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes
2023· 1 cited
Generalized Very High Throughput Unrolled LDPC Layered Decoder
2020· 3 cited
Fault Tolerant Digital Data-Path Design via Control Feedback Loops
Electronics·2020· 2 citedOpen Access
Layered LDPC decoder in-order message access scheduling: a case study
2020
一般化超高スループット非圧延LDPC層状復号器【JST・京大機械翻訳】
IEEE Conference Proceedings·2020
Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller
2019· 4 cited
A Log-Likelihood Ratio based Generalized Belief Propagation
2019· 2 citedOpen Access
Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation
IEEE Transactions on Circuits and Systems I Regular Papers·2018· 26 cited
Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding
2018· 1 cited
Unrolled layered architectures for non-surjective finite alphabet iterative decoders
2017· 3 cited
Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders
2017· 14 cited
Design Trade‐Offs for FPGA Implementation of LDPC Decoders
InTech eBooks·2017· 1 citedOpen Access
Design Trade-offs in Configurable FPGA Architectures for K-Means Clustering
Studies in Informatics and Control·2017· 14 citedOpen Access
On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers
Journal of Circuits Systems and Computers·2017
Reliability analysis of memory centric LDPC decoders under probabilistic storage failures
2016· 1 cited
Cost effective FPGA implementation for hard decision LDPC decoders
2016· 2 cited
Configurable FPGA architecture for hardware-software merge sorting
2016· 3 cited
Variable throughput LDPC decoders using SIMD-based adaptive quantization
2016· 2 cited
FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization
2016· 15 cited
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Frequent Co-authors

Oana Boncalo(44), Mircea Vlăduţiu(13), Mihai Udrescu(11), Lucian Prodan(10), Valentin Savin(9), Sergiu Nimară(5), David Declercq(4), Constantina‐Elena Gavriliu(3), Fakhreddine Ghaffari(3), Emanuel Popovici(3), Mircea Popa(2), Jiaoyan Chen(2), Christian Spagnol(2), Sorin Cotöfană(2), Andrei Hera(2), Cosmin Cernăzanu-Glăvan(2), Marius Marcu(2), Madalin Ghenea(2), Zheng Wang(2), Jan Henrik Weinstock(2)