Ping Lu

Microsoft (United States) — United States

Engineering · Physical Sciences

9h-index396citations62works0.52yr avg
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Research Topics

Advancements in PLL and VCO Technologies(35), Analog and Mixed-Signal Circuit Design(22), Radio Frequency Integrated Circuit Design(19), Photonic and Optical Devices(19), Semiconductor Lasers and Optical Devices(11)

Publications62 total

Fast Frequency-Hopping Digital PLL Solution for Supply Droop Induced Timing Issue
2025
A 6.8-GHz Fractional-N Pulse-Shaper-Based PLL Achieving −269.9-dB FoM <sub>Jitter-N-Area</sub>
IEEE Transactions on Circuits and Systems I Regular Papers·2025
Pre-classification-based multi-model fusion non-intrusive load identification
Journal of Computational Methods in Sciences and Engineering·2024· 1 cited
Insulator Defect Detection Technology Based on Deep Learning
2024
A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC
2024· 1 cited
A Wideband Rotman Lens Design Based on Co-Simulation Technology
2024
Design of a 12-bit 10-GSPS Cryogenic ADC for Quantum Readout
2024· 1 citedOpen Access
Design of a Low-Jitter 10 GHz PLL for a 12-bit 10-GSPS Cryogenic ADC for Quantum Readout in 22FDX
2024· 1 citedOpen Access
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques
IEEE Transactions on Circuits and Systems I Regular Papers·2023· 13 cited
Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface
2023
An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications
2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)·2022· 1 cited
A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET
2022 IEEE International Symposium on Circuits and Systems (ISCAS)·2022
PCB embedded magnetic technology and design implementation
2022 IEEE 2nd International Conference on Power, Electronics and Computer Applications (ICPECA)·2022
A 25.6-27.5GHz Phase-Locked Loop for SerDes Transceiver Clocking in 5nm FinFET
2021· 1 cited
A Time-Domain 147fs<sub>rms 2.5</sub>-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction
IEEE Transactions on Circuits and Systems I Regular Papers·2020· 15 citedOpen Access
Development of a high-k gate stack for atomic-precision advanced manufacturing
OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)·2020Open Access
Performance Evaluation of Four-Reader Array Detection for Two-Dimensional Magnetic Recording
Science of Advanced Materials·2019
Zero-Current-Switching in Full-Bridge DC-DC Converters Based on Activity Auxiliary Circuit
Journal of Power Electronics·2019· 1 cited
A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise
IEEE Journal of Solid-State Circuits·2017· 78 cited
A New Transmitted Reference Pulse Cluster Based Ultra-Wideband Transmitter Design
arXiv (Cornell University)·2017Open Access
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Frequent Co-authors

Pietro Andreani(11), Ying Wu(8), Antonio Liscidini(5), Pietro Andreani(5), Robert Bogdan Staszewski(4), Henrik Sjöland(4), Baogen Sun(4), Minhan Chen(4), Dawei Ye(3), Mina Shahmohammadi(2), Yue Chen(2), Junying Zou(2), Ronan van der Zee(2), Shaishav Desai(2), Muhammad Shakir(2), Mohammed Abdulaziz(2), D. Braga(2), Kushal Das(2), Neil Dick(2), Ken Dyer(2)