Stefanus Mantik

Cadence Design Systems (United States) — United States

Engineering · Physical Sciences

18h-index1.3kcitations27works0.02yr avg
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Research Topics

VLSI and FPGA Design Techniques(19), VLSI and Analog Circuit Testing(17), Advancements in Photolithography Techniques(9), Physical Unclonable Functions (PUFs) and Hardware Security(7), Manufacturing Process and Optimization(4)

Publications27 total

ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules
2019· 45 cited
ISPD 2018 Initial Detailed Routing Contest and Benchmarks
2018· 66 cited
Routing-aware scan chain ordering
ACM Transactions on Design Automation of Electronic Systems·2005· 22 cited
A proposal for routing-based timing-driven scan chain ordering
2004· 4 cited
Effective Iterative Techniques for Fingerprinting Design IP
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2004· 91 cited
Effective Iterative Techniques for
2004
Measurement of inherent noise in EDA tools
2003· 33 cited
Effective iterative techniques for fingerprinting design IP [VLSI CAD]
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)·2003· 27 cited
Routing-aware scan chain ordering
2003· 9 cited
Metrics: automatic data collection infrastructure for continuous ic design process improvement
2003
Implications of area-array I/O for row-based placement methodology
2002· 21 cited
Robust IP watermarking methodologies for physical design
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)·2002· 5 cited
A system for automatic recording and prediction of design quality metrics
2002· 23 cited
On mismatches between incremental optimizers and instance perturbations in physical design tools
2002· 12 cited
Min-max placement for large-scale timing optimization
2002· 62 cited
Min-max placement for large-scale timing optimization
2002· 2 cited
Toward accurate models of achievable routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2001· 27 cited
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2001· 222 cited
On mismatches between incremental optimizers and instance perturbations in physical design tools
International Conference on Computer Aided Design·2000· 14 cited
Requirements for models of achievable routing
2000· 5 cited
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Frequent Co-authors

Andrew B. Kahng(24), Igor L. Markov(9), Miodrag Potkonjak(9), Andrew Caldwell(7), Jennifer L. Wong(5), Paul A. Tucker(4), G. Wolfe(4), Gang Qu(3), Hyun‐Jin Choi(3), Puneet Gupta(3), John Lach(2), William H. Mangione-Smith(2), Huijuan Wang(2), Alex Zelikovsky(2), Gracieli Posser(2), Wing-Kai Chow(2), Yixiao Ding(2), Wenhao Liu(2), Dirk Stroobandt(2), H. Wang(1)