Dwaipayan Biswas

Indian Institute of Science Education and Research, Bhopal — India

Engineering · Physical Sciences

22h-index2.5kcitations97works2.22yr avg
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Research Topics

Non-Invasive Vital Sign Monitoring(17), ECG Monitoring and Analysis(14), EEG and Brain-Computer Interfaces(12), 3D IC and TSV technologies(11), Stroke Rehabilitation and Recovery(10)

Publications97 total

Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-Based Systems-in-Package Using Nanosheet Technology
2025· 1 cited
PPAT for Multi-Die 3D Accelerator Design in Advanced Nanosheet and CFET Technology
2025
Impact of Intrinsic Hydrophobicity of Bile Salts on the Inhibition of Temperature‐Induced Aggregation of Bovine Serum Albumin
ChemPhysChem·2025· 2 cited
SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation
ACM Transactions on Embedded Computing Systems·2025
Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology
arXiv (Cornell University)·2025Open Access
TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering
2025· 1 cited
A Survey of End-to-End Modeling for Distributed DNN Training: Workloads, Simulators, and TCO
arXiv (Cornell University)·2025Open Access
3D SRAM Disaggregation in Advanced CMOS Nodes using Hybrid Bonding Technology
2025
Design Technology Co-Optimization of 3D SRAM Macro in Nanosheet Technology for High-Bandwidth Applications
2025
Late Breaking Results: Thermal Feasibility of Backside Integrated LDOs in 2.5D/3D System-in-Package Using Nanosheet Technology
2025· 1 cited
[Withdrawn] Calibrating DRAMPower Model: A Runtime Perspective from Real-System HPC Measurements
2024Open Access
System Technology Co-Optimization of Cost-Bandwidth Tradeoffs in Network on Chip Through 3D Integration and Backside Signals
2024· 2 cited
Calibrating DRAMPower Model for HPC: A Runtime Perspective from Real-Time Measurements
arXiv (Cornell University)·2024Open Access
Evaluation of a Ferroelectric Capacitor-Based Compute-in-Memory Framework
2024· 3 citedOpen Access
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2024· 4 cited
On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies
2024· 1 cited
Thermal Insights into 3D Packaging of a HighPerformance Server SoC in Advanced Nanosheet Technology
2024· 3 cited
Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet
2024· 7 cited
Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC
2024· 8 cited
DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD
2024Open Access
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Frequent Co-authors

Koushik Maharatna(16), Nick Van Helleputte(15), Amit Acharyya(13), Chris Van Hoof(12), Mario Konijnenburg(10), Madhuri Panwar(8), Michael Jöbges(7), Wim Sijbers(6), Andy Cranny(6), Josy Achner(6), Jasmin Klemke(6), Steffen Ortmann(6), Evangelos B. Mazomenos(5), Shuang Song(5), Roland van Wegberg(5), Qiuyang Lin(5), Francky Catthoor(5), Bram-Ernst Verhoef(4), Chris H. Kim(4), Marian Verhelst(4)