Chorng‐Kuang Wang

Tokyo Institute of Technology — Japan

Engineering · Physical Sciences

21h-index1.3kcitations102works0.02yr avg
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Research Topics

Radio Frequency Integrated Circuit Design(58), Advancements in PLL and VCO Technologies(46), Analog and Mixed-Signal Circuit Design(31), Microwave Engineering and Waveguides(21), Advanced Wireless Communication Techniques(16)

Publications102 total

My Reflections on Akira Matsuzawa’s Years at Tokyo Institute of Technology: An educator
IEEE Solid-State Circuits Magazine·2022
Table of Contents
IEEE Solid-State Circuits Magazine·2022Open Access
2.4 GHz discrete‐time receiver without subsampling mixer
Electronics Letters·2014· 3 citedOpen Access
A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOS
2014· 3 cited
A 379nW 58.5dB SNDR VCO-based ΔΣ modulator for bio-potential monitoring
2013· 3 cited
A CMOS Cantilever-Based Label-Free DNA SoC With Improved Sensitivity for Hepatitis B Virus Detection
IEEE Transactions on Biomedical Circuits and Systems·2013· 36 cited
A 60 GHz wideband active balun using magnitude and phase concurrent correction technique in 65nm CMOS
2012· 6 cited
I/Q imbalance compensation and channel equalization algorithm for MISO-OFDM systems
2012· 2 cited
A fully integrated hepatitis B virus DNA detection SoC based on monolithic polysilicon nanowire CMOS process
2012· 12 cited
A 0.2–2.6 GHz Wideband Noise-Reduction Gm-Boosted LNA
IEEE Microwave and Wireless Components Letters·2012· 21 cited
A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascode
2012· 8 cited
An 80 GHz Wide Tuning Range Push-Push VCO With ${\rm g} _{\rm m}$-Boosted Full-Wave Rectification Technique in 90 nm CMOS
IEEE Microwave and Wireless Components Letters·2012· 33 cited
A 1V 19.3dBm 79GHz power amplifier in 65nm CMOS
2012· 70 cited
An 85-GHz injection-locked frequency divider with current-reuse pre-amplifier technique
2011· 2 cited
A low power W-band PLL with 17-mW in 65-nm CMOS technology
2011· 8 cited
A 90 nm CMOS V-Band Low-Noise Active Balun With Broadband Phase-Correction Technique
IEEE Journal of Solid-State Circuits·2011· 35 cited
A fully-integrated cantilever-based DNA detection SoC in a CMOS Bio-MEMS process
2011· 6 cited
Cost-efficient design and fixed-point analysis of IFFT/FFT processor chip for OFDM systems
2011· 4 cited
Design and analysis of cost-efficient IFFT/FFT processor chip for wireless OFDM systems
2010· 1 cited
A 63 GHz low-noise active balun with broadband phase-correction technique in 90 nm CMOS
2010· 2 cited
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Frequent Co-authors

Chao-Shiun Wang(12), Po-Chiun Huang(7), Chao-Shiun Wang(6), Chien-Chih Lin(5), Muh‐Tian Shiue(4), Juin-Wei Huang(4), Tao-Yao Chang(3), Chih‐Ting Lin(3), Hsiao-Ting Hsueh(3), Hann-Huei Tsai(3), Ying‐Zong Juang(3), Shey‐Shi Lu(3), Chih-Feng Wu(3), Shon-Hang Wen(3), Kun-Da Chu(3), Hua-Chin Lee(3), Kuang-Hu Huang(3), Chen-Yi Huang(3), You-Kuang Chang(2), Yi-Huei Chen(2)