Santosh Kumar Vishvakarma

Indian Institute of Technology Indore — India

Engineering · Physical Sciences

26h-index2.3kcitations240works0.72yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(101), Semiconductor materials and devices(98), Low-power high-performance VLSI design(58), Advanced Memory and Neural Computing(39), Integrated Circuits and Semiconductor Failure Analysis(26)

Publications240 total

C-SIMD: CORDIC-Driven SIMD Processing Element for Resource-Efficient Multi-Precision Deep Learning Inference
IEEE Access·2026Open Access
A 10T SRAM-Based PUF Enhanced by In-Memory Computing for Secure Authentication
2025Open Access
Effects of a yoga-based intervention program on psychological immunity and life satisfaction among armed forces personnel of India: a randomised controlled trial
BMC Psychology·2025Open Access
Gated logic controlled 10T-SRAM for low-power bidirectional ring oscillators
Integration·2025
Res-DPU: Resource-shared Digital Processing-in-memory Unit for Edge-AI Workloads
arXiv (Cornell University)·2025Open Access
ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine
arXiv (Cornell University)·2025Open Access
Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation
arXiv (Cornell University)·2025Open Access
Energy-Optimized 16Kb Digital CIM SRAM Macro Achieving 4.3 TOPS and 112 TOPS/W for High-Precision Neural Network Acceleration in Resource-Constrained Edge Environments
2025Open Access
ReNPU: A Resource-efficient Multi-Mode Neural Processing Unit with Unified Multi-Precision Datapath for Mobile AI Workloads
2025Open Access
ARIES: ADC-Less 3T1R-based nvCIM macro for Edge AI applications
2025Open Access
Retrospective: A CORDIC Based Configurable Activation Function for NN Applications
2025· 1 citedOpen Access
POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration
2025Open Access
POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration
arXiv (Cornell University)·2025Open Access
QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Engine
arXiv (Cornell University)·2025Open Access
SHIFFT: SOA-free Hybrid Interferometric Flip-Flop with Tuned Feedback for High-Speed Applications
2025Open Access
Runtime-Adaptive, NAF-Repurposed Accelerator for Resource-efficient Edge AI Inference
2025Open Access
LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine
2025· 1 cited
Area-Optimized 2D Interleaved Adder Tree Design for Sparse DCIM Edge Processing
2025· 1 cited
Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2025· 5 cited
DARE: Delay and Area-optimized Reconfigurable Edge DPIM Macro
2025Open Access
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Frequent Co-authors

Ambika Prasad Shah(10), Gopal Raut(9), Shailesh Singh Chouhan(7), Pooran Singh(7), Nandakishor Yadav(6), Ankur Beohar(6), C. B. Kushwah(5), Neha Gupta(5), Vishal Sharma(5), Vikas Vijayvargiya(4), Narendra Singh Dhakad(4), Dheeraj Sharma(3), Maisagalla Gopal(3), Sajid Khan(3), Jai Gopal Pandey(3), Bhupendra Singh Reniwal(3), Balwinder Raj(2), Shubham Rai(2), Akash Kumar(2), Gunjan Rajput(2)