Anup Dandapat

National Institute of Technology Meghalaya — India

Engineering · Physical Sciences

13h-index973citations74works1.32yr avg
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Research Topics

Low-power high-performance VLSI design(37), Network Packet Processing and Optimization(25), Analog and Mixed-Signal Circuit Design(23), Advancements in Semiconductor Devices and Circuit Design(15), Numerical Methods and Algorithms(13)

Publications74 total

Achieving superior segmented CAM efficiency with pre-charge free local search based hybrid matcher for high speed applications
Integration·2025
A Segmented Hybrid CAM for High Speed Application Using FinFET
2024
The advanced adder generated using modified square root with AND-OR invert logic
2024
An Approach to Design a Low Power High-Speed Full Adder Circuit Based on Logical Effort
Electronics ETF·2024Open Access
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine
Integration·2024· 9 cited
Design of a Stack Based Compressor for High Speed Computation
2024
CASCAM: Comparative Analysis of Search Operation of FinFET- and MOSFET-Based Content-Addressable Memory
Lecture notes in electrical engineering·2024
A Low Power Partial Precharging based Double Tail Dynamic Comparator
2023Open Access
Low Power Sense Amplifier For A 64×32 Bit Sram Array For IOT Application
2023
SMS-CAM: Shared matchline scheme for content addressable memory
Integration·2022· 12 cited
Design of a 1.29–1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoMT) for GPS and Satellite Navigation
Journal of Circuits Systems and Computers·2022· 3 cited
Modified Baugh Wooley Multiplier using Low Power Compressors
2021 2nd International Conference for Emerging Technology (INCET)·2021· 2 cited
Analysis of the Universal Gates based on the Comparative Factors of Delay Propagation, Average Power Dissipation and Logical Effort
2021 2nd International Conference for Emerging Technology (INCET)·2021· 4 cited
Match‐line control unit for power and delay reduction in hybrid CAM
IET Circuits Devices & Systems·2021· 7 citedOpen Access
Low-power content addressable memory design using two-layer P-N match-line control and sensing
Integration·2020· 8 cited
Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications
IEEE Transactions on Circuits and Systems I Regular Papers·2020· 44 cited
The analogy of matchline sensing techniques for content addressable memory (CAM)
IET Computers & Digital Techniques·2020· 3 citedOpen Access
Pseudo-Static Master-Slave Match-Line Scheme for Sustainable-Performance and Energy-Efficient Content Addressable Memory
2020 IEEE Region 10 Symposium (TENSYMP)·2020· 3 cited
A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM).
Journal of information science and engineering·2020· 2 cited
Design and Implementation of Drivers and Selectors for Content Addressable Memory (CAM)
2019· 3 cited
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Frequent Co-authors

Sandeep Mishra(21), Telajala Venkata Mahendra(18), Prabir Saha(16), Partha Bhattacharyya(14), Sheikh Wasmir Hussain(14), Arindam Banerjee(7), Deepak Kumar(6), D. Kayal(4), Manash Chanda(3), Hafizur Rahaman(3), Chinmoy Sarkar(2), Jyoutishman Saikia(2), Bijoy Kundu(1), Sovan Ghosh(1), Vinay Kumar(1), Abhijit Banerjee(1), Sandip Ghosal(1), Partha Sarkar(1), Debdeep Mukhopadhyay(1), Posiba Mostafa(1)