Muralidaran Vijayaraghavan

Massachusetts Institute of Technology — United States

Computer Science · Physical Sciences

10h-index429citations23works0.02yr avg
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Research Topics

Parallel Computing and Optimization Techniques(16), Embedded Systems Design Techniques(12), Distributed systems and fault tolerance(5), Formal Methods in Verification(4), Interconnection Networks and Systems(4)

Publications23 total

Weak Memory Models with Matching Axiomatic and Operational Definitions
arXiv (Cornell University)·2017Open Access
Kami: a platform for high-level parametric hardware specification and its modular verification
Proceedings of the ACM on Programming Languages·2017· 92 citedOpen Access
An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution
arXiv (Cornell University)·2017Open Access
Taming Weak Memory Models
arXiv (Cornell University)·2016· 3 citedOpen Access
Modular verification of hardware systems
DSpace@MIT (Massachusetts Institute of Technology)·2016· 2 citedOpen Access
A Proof of Correctness for the Tardis Cache Coherence Protocol
arXiv (Cornell University)·2015· 9 citedOpen Access
Modular Deductive Verification of Multiprocessor Hardware Designs
Lecture notes in computer science·2015· 32 cited
A new synthesis procedure for atomic rules containing multi-cycle function blocks
2014· 2 cited
Modular compilation of guarded atomic actions
2013· 5 cited
A general technique for deterministic model-cycle-level debugging
2012
Fast and cycle-accurate modeling of a multicore processor
2012· 24 cited
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID)
2010· 10 cited
A-Port Networks
ACM Transactions on Reconfigurable Technology and Systems·2009· 22 cited
Implementing a fast cartesian-polar matrix interpolator
Formal Methods·2009· 1 cited
Bounded dataflow networks and latency-insensitive circuits
Formal Methods·2009· 33 cited
Implementing a fast cartesian-polar matrix interpolator
2009· 1 cited
Bounded Dataflow Networks and Latency-Insensitive circuits
2009· 35 cited
Theory of composable latency-insensitive refinements
DSpace@MIT (Massachusetts Institute of Technology)·2009· 1 citedOpen Access
High-throughput Pipelined Mergesort
2008· 10 cited
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs
2008· 39 cited
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Frequent Co-authors

Arvind Arvind(14), Nirav Dave(6), Asif Khan(6), Michael Pellauer(5), Man Cheuk Ng(5), Kermin Fleming(4), Myron King(4), Joel Emer(4), Michael Adler(3), Abhinav Agarwal(3), Sizhuo Zhang(3), Adam Chlipala(2), Joonwon Choi(1), Benjamin Sherman(1), Arvind Arvind(1), G. Raghavan(1), Jamey Hicks(1), Silas Boyd-Wickizer(1), Forrest Brewer(1), Xiangyao Yu(1)