Jiang Gong

QuTech — Netherlands

Engineering · Physical Sciences

12h-index352citations18works1.02yr avg
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Research Topics

Advancements in PLL and VCO Technologies(11), Radio Frequency Integrated Circuit Design(10), Photonic and Optical Devices(5), Quantum and electron transport phenomena(5), Analog and Mixed-Signal Circuit Design(4)

Publications18 total

A 4.6-GHz 54.5-fs <sub>rms</sub> PLL-XO Co-Design Featuring a Pulse-Injection XO Driver
IEEE Journal of Solid-State Circuits·2025
19.10 A 4.6GHz ${63.3}\text{fs}_{\text{rms}}$ PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving −255.2dB $\text{FoM}_{\mathrm{J}}$ Including the XO Power and Noise
2025· 1 cited
Cryo-CMOS Bias-Voltage Generation and Demultiplexing at mK Temperatures for Large-Scale Arrays of Quantum Devices
IEEE Transactions on Quantum Engineering·2025· 2 citedOpen Access
A 10-Gb/s 275-fsec Jitter Cryo-CMOS Charge-Sampling CDR for Quantum Computing Application
IEEE Microwave and Wireless Technology Letters·2023· 6 cited
A Cryo-CMOS PLL for Quantum Computing Applications
IEEE Journal of Solid-State Circuits·2022· 33 citedOpen Access
A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit
IEEE Journal of Solid-State Circuits·2022· 15 citedOpen Access
A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications
IEEE Transactions on Circuits and Systems I Regular Papers·2022· 25 citedOpen Access
A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 14 cited
A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB $\mathbf{FoM}_{\mathbf{A}}$ in 22nm FinFET
2022 IEEE International Solid- State Circuits Conference (ISSCC)·2022· 31 cited
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs
2022 IEEE International Solid- State Circuits Conference (ISSCC)·2022· 19 cited
A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and &lt;−54-dBc Spurs Under 50-mVpp Supply Ripple
IEEE Journal of Solid-State Circuits·2021· 19 citedOpen Access
A Low-Jitter and Low-Spur Charge-Sampling PLL
IEEE Journal of Solid-State Circuits·2021· 41 citedOpen Access
A 2.7mW 45fs<sub>rms</sub>-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications
2021· 11 citedOpen Access
A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter, -258.9 dB FOM and -65 dBc Reference Spur
2020· 17 citedOpen Access
19.3 A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications
2020· 50 citedOpen Access
Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers
2019· 50 citedOpen Access
A 1.33 mW, 1.6ps<sub>rms</sub>-Integrated-Jitter, 1.8-2.7 GHz Ring-Oscillator-Based Fractional-N Injection-Locked DPLL for Internet-of-Things Applications
2018· 18 cited
Analysis and Design of a Ring-Oscillator-Based Fractional-N Injection-Locked Digital PLL for IoT Applications
Research Repository (Delft University of Technology)·2017Open Access

Frequent Co-authors

Masoud Babaie(15), Fabio Sebastiano(11), Edoardo Charbon(7), Yue Chen(3), Luc Enthoven(3), Job van Staveren(3), Robert Bogdan Staszewski(3), Bishnu Patra(2), Zhong Gao(2), Jingchu He(2), Martin Fritz(2), Yiyu Shen(2), Zhirui Zong(2), Gerd Spalink(2), Ben Eitel(2), Morteza S. Alavi(2), Can Livanelioglu(2), Long He(2), Sina Arjmandpour(2), Gabriele Atzeni(2)