Jun Sawada

Engineering · Physical Sciences

14h-index6.5kcitations20works3.82yr avg
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Research Topics

Advanced Memory and Neural Computing(10), CCD and CMOS Imaging Sensors(7), Neural Networks and Applications(5), Neuroscience and Neural Engineering(4), Analog and Mixed-Signal Circuit Design(3)

Publications20 total

A Scalable NorthPole System with End-to-End Vertical Integration for Low-Latency and Energy-Efficient LLM Inference
arXiv (Cornell University)·2025Open Access
The NorthPole Validator: A Cycle-Accurate Simulator for HW/SW Codesign of a Prescheduled Neural Inference Accelerator
2025
Breakthrough Edge AI Inference Performance Using Northpole in 3U Vpx Form Factor
2024· 2 cited
Breakthrough Low-Latency, High-Energy-Efficiency LLM Inference Performance Using NorthPole
2024· 3 cited
11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip
2024· 14 cited
Neural inference at the frontier of energy, space, and time
Science·2023· 85 cited
IBM NorthPole Neural Inference Machine
2023· 10 cited
TrueNorth: Accelerating From Zero to 64 Million Neurons in 10 Years
Computer·2019· 231 cited
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications
IEEE International Conference on High Performance Computing, Data, and Analytics·2016· 43 cited
TrueNorth Ecosystem for Brain-Inspired Computing: Scalable Systems, Software, and Applications
2016· 60 citedOpen Access
TrueNorth: A High-Performance, Low-Power Neurosynaptic Processor for Multi-Sensory Perception, Action, and Cognition
2016· 18 cited
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2015· 1.6k cited
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100,000× Reduction in Energy-to-Solution
2014· 73 cited
A million spiking-neuron integrated circuit with a scalable communication network and interface
Science·2014· 4.0k cited
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores
2013· 236 cited
A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
2007· 143 cited
Limited switch dynamic logic circuits for high-speed low-power circuit design
IBM Journal of Research and Development·2006· 20 cited
Design of Shifting and Permutation Units using LSDL Circuit Family
2006· 2 cited
An 8Ghz floating-point multiply
2005· 19 cited
A double precision floating point multiply
2003· 18 cited

Frequent Co-authors

John V. Arthur(15), Andrew S. Cassidy(15), Filipp Akopyan(15), Dharmendra S. Modha(15), W. P. Risk(14), Brian Taba(13), Pallab Datta(13), Arnon Amir(12), Myron Flickner(12), Steven K. Esser(11), Michael DeBole(10), Tapan K. Nayak(10), Kai Schleupen(9), Yutaka Nakamura(8), Carlos Ortega Otero(8), Paul Merolla(7), Rodrigo Alvarez-Icaza(7), Bryan L. Jackson(7), Peter J. Carlson(7), Guillaume Garreau(7)