C. Traver

Union College — United States

Engineering · Physical Sciences

9h-index201citations35works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(13), Embedded Systems Design Techniques(10), Parallel Computing and Optimization Techniques(6), VLSI and Analog Circuit Testing(6), Engineering Education and Pedagogy(6)

Publications35 total

Predictive Analysis of Basketball Shots from Inertial Data Using Machine Learning
2025
International Robotics Design Competitions: Potential And Pitfalls
2024Open Access
IEEE Real World Engineering Projects (RWEP)
2020· 1 citedOpen Access
Fostering Innovation through the Integration of Engineering and Liberal Education
2020· 10 cited
A Freshman Engineering Course Which Introduces Engineering Design And Engineering Fundamentals In The Context Of A Unifying Theme
2020· 5 citedOpen Access
Women Engineers In Advanced Academic Positions (Weaap)
2020Open Access
Integration Of Engineering And The Liberal Arts: A Two Way Street
2020· 9 citedOpen Access
Introducing Freshmen To Engineering Design: Weather Station Project
2020· 1 citedOpen Access
Special session - inventive courses: Blending engineering and the liberal arts
2009· 2 cited
P.O. Pistilli Undergraduate Scholarships for Advancement in Computer Science and Electrical Engineering
2008
Jan Willis - Senior Vice President, Industry Alliances, Cadence Design Systems, Inc. For her significant contributions in helping women advance in the field of EDA technology. The P. O. Pistilli Undergraduate Scholarships for Advancement in Computer Science and Electrical Engineering
2007
Asic Architectures
2005
A Coarse-Grain Phased Logic CPU
IEEE Transactions on Computers·2005· 8 cited
Early evaluation for performance enhancement in phased logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2005· 19 cited
Work in progress: multidisciplinary engineering project abroad
2005· 1 cited
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
2004· 7 cited
Asynchronous rate divider and multiplier designs for LEDR logic
Electronics Letters·2004
Two-phase micropipeline control wrapper with early evaluation
Electronics Letters·2004· 4 cited
Fast two-phase micropipeline control wrapper for standard cell implementation
Electronics Letters·2004· 2 cited
A coarse-grain phased logic CPU
2003· 9 cited
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Frequent Co-authors

R.B. Reese(12), Mitchell A. Thornton(11), David Hemmendinger(2), Aydan M. Erkmen(2), K. Fazel(2), R. Auletta(2), A. Erden(1), Ronald Bucinell(1), Leila Notash(1), Douglass Klein(1), Borjana Mikic(1), Atsushi Akera(1), Steven B. Shooter(1), Ari W. Epstein(1), David D. Gillette(1), K. Fazel(1), Jean-Pierre Klein(1), Bob Reese(1), Mutlu Aydin(1), Lun Li(1)