Paolo Mantovani

Columbia University — United States

Computer Science · Physical Sciences

15h-index677citations43works6.02yr avg
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Research Topics

Parallel Computing and Optimization Techniques(26), Embedded Systems Design Techniques(20), Interconnection Networks and Systems(18), VLSI and Analog Circuit Testing(7), Low-power high-performance VLSI design(5)

Publications43 total

A wireless subdural-contained brain–computer interface with 65,536 electrodes and 1,024 channels
Nature Electronics·2025· 2 citedOpen Access
EPOCHS-1: A 12 nm Highly Heterogeneous Open-Source SoC With Distributed Coin-Based Power Management and Integrated Hybrid Voltage Regulation
IEEE Journal of Solid-State Circuits·2025
Mozart: Taming Taxes and Composing Accelerators with Shared-Memory
2024· 1 cited
Stable, chronic in-vivo recordings from a fully wireless subdural-contained 65,536-electrode brain-computer interface device
2024· 11 citedOpen Access
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
2024· 16 cited
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs
IEEE Design and Test·2023· 4 cited
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design·2022· 7 cited
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)·2022· 24 cited
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP
arXiv (Cornell University)·2022· 7 citedOpen Access
Table of Contents
IEEE Micro·2021Open Access
Accelerator Integration for Open-Source SoC Design
IEEE Micro·2021· 25 cited
sld-columbia/esp: 2021.1.1
Zenodo (CERN European Organization for Nuclear Research)·2021· 1 citedOpen Access
Agile SoC development with open ESP
2020· 87 citedOpen Access
Agile SoC Development with Open ESP : Invited Paper
International Conference on Computer Aided Design·2020· 8 cited
HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis
2020· 19 cited
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs
2019· 11 cited
Teaching Heterogeneous Computing with System-Level Design Methods
2019· 10 citedOpen Access
Runtime reconfigurable memory hierarchy in embedded scalable platforms
2019· 5 cited
Accelerators and Coherence: An SoC Perspective
IEEE Micro·2018· 33 cited
NoC-Based support of heterogeneous cache-coherence models for accelerators
Networks-on-Chips·2018· 13 cited
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Frequent Co-authors

Luca P. Carloni(34), Davide Giri(18), Giuseppe Di Guglielmo(15), Emilio G. Cota(8), Joseph D. Zuckerman(8), Christian Pilato(8), Luca Piccolboni(7), Kenneth L. Shepard(7), Michele Petracca(5), Kevin Tien(5), Tianyu Jia(5), Maico Cassel dos Santos(5), Gabriele Tombesi(5), John-David Wellman(5), David Brooks(5), Gu-Yeon Wei(5), Kuan-Lin Chiu(4), Guy Eichler(4), Erik Jens Loscalzo(4), Jeff Zhang(4)