S.W. Bollinger

Virginia Tech — United States

Computer Science · Physical Sciences

6h-index249citations11works0.02yr avg
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Research Topics

VLSI and Analog Circuit Testing(6), Integrated Circuits and Semiconductor Failure Analysis(6), Low-power high-performance VLSI design(5), Parallel Computing and Optimization Techniques(2), Interconnection Networks and Systems(2)

Publications11 total

ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS
2005· 34 cited
Parallel processing in a logical area network: a case study
2003
An investigation of circuit partitioning for parallel test generation
2003· 2 cited
Classification of bridging faults in CMOS circuits: experimental results and implications for test
2002· 9 cited
Circuit-level classification and testability analysis for CMOS faults
2002· 6 cited
Design planning for high-performance ASICs
IBM Journal of Research and Development·1996· 30 cited
Test generation for I/sub DDQ/ testing of bridging faults in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·1994· 25 cited
Hierarchical test generation for CMOS circuits
VTechWorks (Virginia Tech)·1992· 4 citedOpen Access
Heuristic technique for processor and link assignment in multicomputers
IEEE Transactions on Computers·1991· 72 cited
Processor and link assignment using simulated annealing
VTechWorks (Virginia Tech)·1988Open Access
Processor and Link Assignment in Multicomputers Using Simulated Annealing.
Proceedings of the International Conference on Parallel Processing·1988· 67 cited

Frequent Co-authors

Scott F. Midkiff(8), J. Sayah(1), Rohini Gupta(1), D. D. Sherlekar(1), P. S. Honsinger(1), Jitendra Apte(1), H. H. Chen(1), S. Dasgupta(1), E. P. Hsieh(1), Andrew D. Huber(1), Eamon Hughes(1), Z. M. Kurzum(1), Vasant B. Rao(1), T. Tabtieng(1), V. Valijan(1), Di Yang(1)