Mudit Bhargava

Intel (United States) — United States

Computer Science · Physical Sciences

14h-index700citations42works1.72yr avg
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Research Topics

Physical Unclonable Functions (PUFs) and Hardware Security(13), Semiconductor materials and devices(12), Integrated Circuits and Semiconductor Failure Analysis(11), Low-power high-performance VLSI design(9), Advanced Memory and Neural Computing(6)

Publications42 total

Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration
2025
Next-Generation Flexible Memristor Devices for Sensing and Computing, Storage Applications
2025Open Access
An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications
2024· 5 cited
A survey of Digital Manufacturing Hardware and Software Trojans
arXiv (Cornell University)·2023· 1 citedOpen Access
Cryo-Computing for Infrastructure Applications: A Technology-to-Microarchitecture Co-optimization Study
2022 International Electron Devices Meeting (IEDM)·2022· 18 cited
Early Design/Technology Exploration of BEOL Options for Hybrid Wafer Bonded Split-SRAM
IEEE Transactions on Electron Devices·2022· 1 cited
Graphics vs Gameplay: A Comparative Analysis in Gaming
2022 2nd International Conference on Intelligent Technologies (CONIT)·2022· 1 cited
Buried Interconnects for Sub-5 nm SRAM Design
IEEE Transactions on Electron Devices·2022· 9 cited
A Fokker-Planck Solver to Model MTJ Stochasticity
2021· 1 citedOpen Access
Towards Development of Performance Metrics for Benchmarking SLAM Algorithms
Journal of Physics Conference Series·2021· 3 citedOpen Access
A Compact Model for Scalable MTJ Simulation
arXiv (Cornell University)·2021· 1 citedOpen Access
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS
2021· 5 cited
Buried Bitline for sub-5nm SRAM Design
2020· 10 cited
A high-density logic-on-logic 3DIC design using face-to-face hybrid wafer-bonding on 12nm FinFET process
2020· 14 cited
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling
arXiv (Cornell University)·2020· 9 citedOpen Access
Enhanced 3D Implementation of an Arm<sup>®</sup> Cortex<sup>®</sup>-A Microprocessor
2019· 11 cited
Performance Enhancement of MEMS based Piezoelectric Pressure Sensor using Multistep Configuration
2019· 1 cited
A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms
2019· 2 cited
On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators
2019· 55 cited
Secure hardware-entangled field programmable gate arrays
Journal of Parallel and Distributed Computing·2019· 2 cited
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Frequent Co-authors

Ken Mai(19), Brian Cline(8), Cagla Cakir(5), Mark P. McCartney(5), Rahul Mathur(4), Jaydeep P. Kulkarni(4), YK Chong(3), Daniel Fisher(3), Frank Frederick(3), Heath Perry(3), Daniel M. Smith(3), Alberto Cestero(3), Norman Robson(3), Saurabh Sinha(3), Andy W. Chen(2), Sriram Thyagarajan(2), S. C. H. Hung(2), Pranavi Chandupatla(2), Xiaoqing Xu(2), Shairfe Muhammad Salahuddin(2)