Hyunjoon Kim

SLAC National Accelerator Laboratory — United States

Engineering · Physical Sciences

15h-index877citations33works1.52yr avg
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Research Topics

Advanced Memory and Neural Computing(20), Ferroelectric and Negative Capacitance Devices(16), CCD and CMOS Imaging Sensors(7), Semiconductor materials and devices(4), Quantum Computing Algorithms and Architecture(4)

Publications33 total

A Single-Ended SAR ADC with Low-Energy Differential Switching for X-Ray Imagers
2024· 1 cited
SparkPix-RT2: The design of a 192 × 168 pixel detector ASIC with on-chip data processing for ultra-fast photon science
2024
Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout
arXiv (Cornell University)·2024Open Access
The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results
Journal of Instrumentation·2024· 5 citedOpen Access
DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC
2023· 8 cited
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
IEEE Transactions on Circuits and Systems I Regular Papers·2023· 28 cited
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks
IEEE Transactions on Circuits and Systems I Regular Papers·2023· 33 cited
SRAM-Based Processing-in-Memory (PIM)
2022· 4 cited
Backgrounds
2022
A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
2022 IEEE International Symposium on Circuits and Systems (ISCAS)·2022· 6 cited
A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications
IEEE Transactions on Circuits and Systems I Regular Papers·2022· 23 cited
A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices
IEEE Journal on Emerging and Selected Topics in Circuits and Systems·2022· 31 cited
SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks
IEEE Transactions on Circuits and Systems I Regular Papers·2022· 36 cited
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems
IEEE Journal of Solid-State Circuits·2022· 34 cited
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems
IEEE Journal of Solid-State Circuits·2022· 36 cited
Hardware and algorithm co-optimization for energy-efficient machine learning integrated circuits
2022· 1 citedOpen Access
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems
2021· 10 cited
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks
IEEE Journal of Solid-State Circuits·2021· 165 cited
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks
IEEE Transactions on Circuits and Systems I Regular Papers·2020· 82 cited
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length
2020· 3 cited
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Frequent Co-authors

Bongjin Kim(16), Tony Tae-Hyoung Kim(13), Taegeun Yoo(6), Junjie Mu(6), Yuqi Su(5), Kunsoo Park(4), Chengshuo Yu(4), Lorenzo Rota(4), A. Dragone(4), Qian Chen(3), Lu Lu(3), Bojan Marković(3), Aseem Gupta(3), Geonmo Gu(2), Vishal Sharma(2), Yuzong Chen(2), Filippo Mele(2), Pietro King(2), A. Peña Perez(2), D. Doering(2)