Huaguo Liang

Hefei University of Technology — China

Computer Science · Physical Sciences

23h-index2.3kcitations295works2.22yr avg
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Research Topics

VLSI and Analog Circuit Testing(96), Integrated Circuits and Semiconductor Failure Analysis(84), Radiation Effects in Electronics(59), Semiconductor materials and devices(46), Interconnection Networks and Systems(46)

Publications295 total

Hi-ILT: A hybrid End-to-End framework of lightweight hierarchical VAE and physics-Guided ILT for inverse lithography technology
Optics and Lasers in Engineering·2026
FTPUF:Feedback structure of TERO PUF for high reliability
Integration·2025
Dual-state Hybrid PUF for Resistance to Machine Learning Attacks
ACM Transactions on Design Automation of Electronic Systems·2025
Prebond Test of TSV Based on Voltage Skew Amplification
IEEE Transactions on Circuits & Systems II Express Briefs·2025
IRCA-TRNG: A Lightweight Dual-Ring Chaotic TRNG With Perturbation Refresh for High Throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2025· 1 cited
A reliability-noise-delay quantification method for APUF physical modeling and CRPs screening
Microelectronics Journal·2025
A QNU hardened latch design with low cost high stability and high performance
Microelectronics Journal·2025
Design of a Dynamic Obfuscation-Based Strong PUF Resistant to Modeling Attacks
2025
A Block-Group-Based Redundant TSV Architecture for Clustered Faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2025
Integrative multi-omics analysis reveals the interaction mechanisms between gut microbiota metabolites and ferroptosis in rheumatoid arthritis
Frontiers in Immunology·2025Open Access
Semisupervised Lithography Hotspot Detection Model Based on Dual-Branch Auxiliary Classification
IEEE Transactions on Semiconductor Manufacturing·2025
Semi-supervised lithography hotspot detection based on feature fusion and residual attention
Integration·2025
High-performance, low-area-overhead, and low-delay triple-node-upset self-recoverable latch design based on stacked transistors
Microelectronics Reliability·2025
Ring Oscillator-Based PreBond TSV Testing Method With Classification and Grading of Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2025
Fabdb: a low-latency fault-tolerant architecture based on dynamic bypass for network-on-chip
The Journal of Supercomputing·2025· 1 cited
Improve SAC in PUFs: Metric, Analysis, Algorithm, and Application
IEEE Internet of Things Journal·2025
RHT_NoC: A Reconfigurable Hybrid Topology Architecture for Chiplet-Based Multicore System
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2025· 1 cited
BF PUF: A Modeling Attack-Resistant Strong PUF Based on Bent Functions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2025· 4 cited
TNURML: Triple-Node-Upset-Recovery Magnetic Latch Design with Non-Volatility for Aerospace Applications
2025Open Access
A TSV Misalignment-Based Repair Architecture in 3-D Chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2025· 1 cited
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Frequent Co-authors

Zhengfeng Huang(36), Maoxiang Yi(19), Yingchun Lu(16), Aibin Yan(15), Tianming Ni(14), Cuiyun Jiang(11), Liang Yao(9), Sybille Hellebrand(5), Yiming Ouyang(5), Hao Chang(5), Xiaoqing Wen(5), Qi Xu(4), Hans-Joachim Wunderlich(4), Xiumin Xu(4), Haochen Qi(4), Xinyu Wang(3), Tai Song(3), Dawen Xu(3), Yiming Ouyang(3), Xiangsheng Fang(3)