Srikanth Venkataraman

Intel (United States) — United States

Computer Science · Physical Sciences

12h-index542citations48works0.02yr avg
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Research Topics

VLSI and Analog Circuit Testing(41), Integrated Circuits and Semiconductor Failure Analysis(38), Radiation Effects in Electronics(10), VLSI and FPGA Design Techniques(7), Semiconductor materials and devices(6)

Publications48 total

Design technology co-optimization for early intercept on maturing process nodes
2025
Generating Storage-Aware Test Sets Targeting Several Fault Models
2024
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults
2022· 1 cited
Defect-Oriented Test: Effectiveness in High Volume Manufacturing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2020· 29 citedOpen Access
LFSR-Based Test Generation for Reduced Fail Data Volume
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2020· 3 cited
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design
ACM Transactions on Design Automation of Electronic Systems·2019· 2 citedOpen Access
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults
2019· 5 cited
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines
2019· 5 cited
Diagnosis of Scan Logic and Diagnosis Driven Failure Analysis[1]
ASM International eBooks·2019
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests
2018· 19 cited
Interconnect-aware tests to complement gate-exhaustive tests
2018· 2 cited
Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure
2017· 4 cited
Test Modification for Reduced Volumes of Fail Data
ACM Transactions on Design Automation of Electronic Systems·2017· 7 cited
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2016· 4 cited
A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction
2016· 10 cited
A novel diagnostic test generation methodology and its application in production failure isolation
2016· 11 cited
Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm
2016· 14 cited
A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction
IEEE Conference Proceedings·2016
Diagnostic Fail Data Minimization Using an N-Cover Algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2015· 9 cited
Built-in generation of functional broadside tests considering primary input constraints
2014
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Frequent Co-authors

Irith Pomeranz(19), M. Enamul Amyeen(13), W.K. Fuchs(4), Dongok Kim(4), Shraddha Bodhe(4), Arani Sinha(4), Sreejit Chakravarty(3), J.H. Patel(3), S.M. Reddy(3), Nai‐Xing Wang(3), Enamul Amyeen(3), I. Hartanto(2), E.M. Rudnick(2), Hari Addepalli(2), Suriyaprakash Natarajan(2), Ruchir Puri(2), Steve Griffith(2), Ankush Oberai(2), Greg Yeric(2), Walter Ng(2)