Gai Liu

Soochow University — Taiwan

Computer Science · Physical Sciences

16h-index1.3kcitations30works0.02yr avg
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Research Topics

Parallel Computing and Optimization Techniques(13), Embedded Systems Design Techniques(13), Interconnection Networks and Systems(9), VLSI and FPGA Design Techniques(6), Viral Infections and Outbreaks Research(6)

Publications30 total

Identification and Characterization of a Metal Binding-Independent Rift Valley Fever Virus Endonuclease Inhibitor
ACS Infectious Diseases·2025Open Access
Design and Experimental Study of Parallel Hip Joint
2025
FPGA-Specific Compilers
2024
FPGA HLS Today: Successes, Challenges, and Opportunities
ACM Transactions on Reconfigurable Technology and Systems·2022· 156 citedOpen Access
FPGA-Specific Compilers
2022
Special Session Program Committee
2020Open Access
Rapid Generation of High-Quality RISC-V Processors from Functional Instruction Set Specifications
2019· 8 cited
PIMAP 並列化反復最適化によるLUTベース技術マッピング改善のための柔軟なフレームワーク【JST・京大機械翻訳】
ACM Transactions on Reconfigurable Technology and Systems·2019
PIMap
ACM Transactions on Reconfigurable Technology and Systems·2018· 11 citedOpen Access
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
IEEE Micro·2018· 86 cited
DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation
2018
A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation
2018· 19 cited
Rosetta
2018· 116 cited
Statistically certified approximate logic synthesis
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)·2017· 30 cited
Enabling adaptive loop pipelining in high-level synthesis
2017· 18 cited
Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2017· 12 cited
A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping
2017· 26 citedOpen Access
A Parallel Bandit-Based Approach for Autotuning FPGA Compilation
2017· 46 citedOpen Access
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis
2017· 40 citedOpen Access
Improving high-level synthesis with decoupled data structure optimization
2016· 13 citedOpen Access
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Frequent Co-authors

Zhiru Zhang(21), Ritchie Zhao(8), Steve Dai(7), Daisy W. Leung(6), Gaya K. Amarasinghe(6), Christopher F. Basler(5), Priya Luthra(4), Reed S. Shabman(4), Christopher Batten(4), Mingxing Tan(4), Dominika Borek(3), Nitish Srivastava(3), Yi‐Hsiang Lai(3), S Srinath(3), Parameshwaran Ramanan(2), Chad E. Mire(2), Benjamin Yen(2), Thomas W. Geisbert(2), Jennifer M. Binning(2), Ariel Endlich-Frazier(2)