Juinn-Dar Huang

National Yang Ming Chiao Tung University — Taiwan

Computer Science · Physical Sciences

17h-index994citations129works5.32yr avg
OpenAlex↗ORCID↗Google Scholar↗Lab page↗

Accepting Students?

No reports yet. Know if this professor is taking students?

Research Topics

Embedded Systems Design Techniques(35), Electrowetting and Microfluidic Technologies(28), Interconnection Networks and Systems(27), VLSI and FPGA Design Techniques(27), VLSI and Analog Circuit Testing(26)

Publications129 total

Expertfuse: A huffman tree-based gradual expert integration framework for MoE models
Neural Networks·2025
An Accurate and Compact Design Integrating Seven Common Nonlinear Functions in Deep Learning
2025
Codeword Decomposition and Recoding Based Lossless Model Compression Algorithm and Its VLSI Decompressor Design
2025
SMILE-UHURA Challenge -- Small Vessel Segmentation at Mesoscopic Scale from Ultra-High Resolution 7T Magnetic Resonance Angiograms
arXiv (Cornell University)·2024· 3 citedOpen Access
Enhancing Brain Tumor Segmentation with Deep Supervision and Attention Mechanisms: Advances in the nnU-Net Framework
2024· 1 cited
A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications
2024· 1 cited
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems
2024
Diabetic foot ulcers segmentation challenge report: Benchmark and analysis
Medical Image Analysis·2024· 37 citedOpen Access
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
2023
Hardware-Friendly Activation Function Designs and Its Efficient VLSI Implementations for Transformer-Based Applications
2023· 3 cited
Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning
2023· 5 cited
Capture the Devil in the Details via Partition-then-Ensemble on Higher Resolution Images
Lecture notes in computer science·2023· 5 cited
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization
ACM Transactions on Design Automation of Electronic Systems·2022· 2 cited
An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability
2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)·2022· 2 cited
Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets
2022· 3 cited
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy
2022· 1 cited
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)·2022· 7 cited
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip
2021
An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing
2021· 7 cited
Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation
Electronics·2021· 1 citedOpen Access
page 1 of 7Next →

Frequent Co-authors

Jing-Yang Jou(15), Chia‐Hung Liu(10), Wen-Zen Shen(5), Sukanta Bhattacharjee(4), Bhargab B. Bhattacharya(4), Che-Hua Shih(4), Ting-Wei Chiang(3), Jie-Hong R. Jiang(3), Yu-Ru Hong(3), Sudip Roy(2), Yung-Han Chen(2), Yi-Jen Ju(2), Hao‐Han Chang(2), Tung-Che Liang(2), Chi‐Hui Lee(2), Chi-Mei Huang(2), Bu-Ching Lin(2), Geeng-Wei Lee(2), Ya-Shih Huang(2), Chia-I Chen(2)