Rakesh Patel

Engineering · Physical Sciences

9h-index1.1kcitations34works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(12), VLSI and Analog Circuit Testing(9), Advancements in PLL and VCO Technologies(7), Parallel Computing and Optimization Techniques(6), Semiconductor materials and devices(6)

Publications34 total

Power Analysis and Optimization from Circuit to Register-Transfer Levels
2018· 4 cited
Performance enhancement for 14nm high volume manufacturing microprocessor and system on a chip processes
2016· 14 cited
Power Analysis and Optimization from Circuitto Register-Transfer Levels
2016
Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing
2015· 67 cited
Neuroendocrine Considerations in the Rehabilitation of a Patient With Pituitary Apoplexy
Topics in Geriatric Rehabilitation·2015
A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size
2014· 522 cited
TECHNOLOGY The Screen of the Future E-Paper
2014
Session details: 3-D IC design
2011
The bacteriological analysis and health risks in the urban estuary of St. George's Bay, Grenada, West Indies.
PubMed·2010· 4 cited
Nonlinear behavior study in digital bang-bang PLL
2009· 3 cited
Low Power Design for Microprocessors and System on Chip: Nanometer and System-Level Design
2009
ディジタル,バンバン位相同期ループ(PLL)における非線形挙動の研究
Custom Integrated Circuits Conference·2009
Session 21 - Leveraging the third Dimension
2008
Serial Protocol Compliance of an FPGA-Integrated Mixed-Signal
2007
Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller
2007· 3 cited
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A
2007· 4 cited
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs
2006· 1 cited
A signal integrity-based link performance simulation platform
2006· 9 cited
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops
2006· 8 cited
Multi-protocol embedded PCS IP in a FPGA-SOC
2006· 1 cited
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Frequent Co-authors

William Bereza(5), K. Fischer(3), Ik Kyeong Jin(3), C. Pelto(3), P. S. Plekhanov(3), Vivek Tiwari(3), Vinson Chan(3), R. Venkata(3), Chong Lee(3), A. A. Zaliznyak(3), W. Walter Fergusson(3), S. Natarajan(2), M. Agostinelli(2), M. Bost(2), V. Chikarmane(2), Qundong Fu(2), M. Haran(2), M. Heckscher(2), Pulkit Jain(2), M. B. Prince(2)