Y.H. Chan

University of California, Riverside — United States

Engineering · Physical Sciences

17h-index905citations52works1.22yr avg
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Research Topics

Low-power high-performance VLSI design(28), Semiconductor materials and devices(20), VLSI and Analog Circuit Testing(20), Advancements in Semiconductor Devices and Circuit Design(13), Integrated Circuits and Semiconductor Failure Analysis(12)

Publications51 total

An Investigative study of methods for Retinal Image Registration
2025Open Access
#ECR-Paper-03 VESPAR: quantitative analysis of the retinal vasculature using a novel segmentation algorithm to enable gene-phenotype association studies in a cohort of 3,944 patients with inherited retinal diseases
2025Open Access
Quantification of Optical Coherence Tomography Features in >3500 Patients with Inherited Retinal Disease Reveals Novel Genotype-Phenotype Associations
2025· 2 citedOpen Access
Performance, efficiency, and cost analysis of wafer-scale AI accelerators vs. single-chip GPUs
Device·2025· 4 citedOpen Access
Breaking the Reviewer: Assessing the Vulnerability of Large Language Models in Automated Peer Review Under Textual Adversarial Attacks
2025· 1 citedOpen Access
Deep Learning-based Intraoperative Video Analysis for Cataract Surgery Instrument Identification
2024
IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors
IBM Journal of Research and Development·2018· 8 cited
Characterization of Dynamic Laser Stimulation Approach to Locate Memory Fails Using EeLADA
Proceedings - International Symposium for Testing and Failure Analysis·2017
A Detailed Analysis Scheme to Interpret Multiple Photon Emissions Micrograph for Improved Diagnostic Resolution on Open Defects
Proceedings - International Symposium for Testing and Failure Analysis·2017
Experimental Demonstration of the Effects of Laser Pulse Duration on SEU and LADA in CMOS Devices
Proceedings - International Symposium for Testing and Failure Analysis·2016· 1 cited
Optimization of EeLADA for Circuit Logic Defect Localization Using Defect Simulation
Proceedings - International Symposium for Testing and Failure Analysis·2016· 1 cited
IBM z13 circuit design and methodology
IBM Journal of Research and Development·2015· 7 cited
4.1 22nm Next-generation IBM System z microprocessor
2015· 25 cited
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module
IEEE Journal of Solid-State Circuits·2013· 30 cited
7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor
2013· 4 cited
5.5GHz system z microprocessor and multi-chip module
2013· 18 cited
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System
IEEE Journal of Solid-State Circuits·2011· 30 cited
Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor
2011· 5 cited
Tester-Driven Dynamic Laser Stimulation for Hard Functional Failure
Proceedings - International Symposium for Testing and Failure Analysis·2010· 2 cited
The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane
IEEE Design & Test of Computers·2010· 12 cited
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Frequent Co-authors

D. Plass(13), L. Sigal(12), Brian Curran(10), W. Huott(10), M. Mayo(8), J. Warnock(7), Uma Srinivasan(6), D. Rodko(6), S. Wilson(6), Seán Carey(6), Antonio Pelella(6), P. J. Camporese(5), R. M. Averill(5), Ching-Te Chuang(5), S. P. Kowalczyk(5), Yiu-Hing Chan(5), S.H. Goh(5), Pramod Kumar Patel(4), Charles F. Webb(4), Ruchir Puri(4)