Young-Ho Kwak

Korea Innotech (South Korea) — South Korea

Engineering · Physical Sciences

8h-index216citations18works0.02yr avg
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Research Topics

Advancements in PLL and VCO Technologies(16), Radio Frequency Integrated Circuit Design(8), Analog and Mixed-Signal Circuit Design(7), Photonic and Optical Devices(5), Semiconductor Lasers and Optical Devices(5)

Publications18 total

Optimizing Wireless BMS Communication With Multilayer Broadband Antenna Technology
2025
A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOS
IEEE Transactions on Circuits and Systems I Regular Papers·2024
A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS
IEEE Transactions on Circuits & Systems II Express Briefs·2023· 1 cited
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process
IEEE Transactions on Circuits and Systems I Regular Papers·2013· 10 cited
10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2012· 2 cited
A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection
IEEE Transactions on Circuits and Systems I Regular Papers·2012· 30 cited
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile
IEEE Journal of Solid-State Circuits·2012· 20 cited
250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 $\mu$m CMOS
IEEE Journal of Solid-State Circuits·2011· 12 cited
A 0.076mm<sup>2</sup> 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS
2011· 2 cited
An all digital time amplifier with interpolation scheme for low gain variation
2010· 1 cited
250Mbps-5Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13
2010· 2 cited
A $\hbox{Gb/s}+$ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time
IEEE Transactions on Circuits & Systems II Express Briefs·2010· 26 cited
A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC
2009· 8 cited
A slew-rate controlled output driver with one-cycle tuning time
2008
A One-Cycle Lock Time Slew-Rate-Controlled Output Driver
2007· 24 cited
A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling
IEEE Journal of Solid-State Circuits·2006· 65 cited
Low-Noise High-Speed Slew-Rate Controlled Output Driver with One-Cycle Lock Time
ICEIC : International Conference on Electronics, Informations and Communications·2006
A CMOS DLL-based 120MHz to 1.8GHz clock generator for dynamic frequency scaling
2005· 13 cited

Frequent Co-authors

Chulwoo Kim(12), Inhwa Jung(7), Minyoung Song(5), Sewook Hwang(4), Chulwoo Kim(2), Sang‐Yoon Lee(2), Hyung-Rok Lee(2), Byoung-Joo Yoo(2), Daeyun Shim(2), Deog‐Kyoon Jeong(2), Sunghoon Ahn(2), Wookjin Shin(2), Hyeongmin Seo(2), Sangwan Lee(2), Dong-Ho Choi(2), Soon-Jae Won(2), Jaeduk Han(2), Jihun Kim(1), Moonil Kim(1), Sang‐Woo Kim(1)