C. Visweswariah

IBM Research - Thomas J. Watson Research Center — United States

Engineering · Physical Sciences

18h-index2.1kcitations33works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(28), VLSI and FPGA Design Techniques(23), VLSI and Analog Circuit Testing(16), Advancements in Semiconductor Devices and Circuit Design(4), Embedded Systems Design Techniques(4)

Publications33 total

Managing uncertainty in electricity generation and demand forecasting
IBM Journal of Research and Development·2016· 13 cited
Optimal Test Margin Computation for At-Speed Structural Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2009· 10 cited
Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2009
Compact modeling of variational waveforms
Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design·2007· 11 cited
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2006· 30 citedOpen Access
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2006· 226 cited
Criticality computation in parameterized statistical timing
Proceedings - ACM IEEE Design Automation Conference·2006· 11 cited
Gate sizing using incremental parameterized statistical timing analysis
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.·2005· 48 cited
Stepsize Control in Piecewise Approximate Circuit Simulation
2005
Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions
Proceedings. 42nd Design Automation Conference, 2005.·2005· 20 cited
The impact of variability on design methodology
2005
First-order incremental block-based statistical timing analysis
2004· 653 cited
Is statistical timing statistically significant?
2004
Death, taxes and failing chips
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)·2004· 66 cited
Statistical timing for parametric yield prediction of digital integrated circuits
2003· 128 cited
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)·2003· 15 cited
Piecewise approximate circuit simulation
2003· 19 cited
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th conference on Design automation - DAC '03·2003· 47 cited
Optimization of custom MOS circuits by transistor sizing
2002· 41 cited
Incorporation of inductors in piecewise approximate circuit simulation
2002· 3 cited
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Frequent Co-authors

Kerim Kalafala(5), V. Zolotov(5), R.A. Rohrer(4), N. Venkateswaran(3), J.A.G. Jess(3), Srinath R. Naidu(3), Ria Otten(3), Andrew R. Conn(3), Andrew R. Conn(3), R.A. Haring(3), Jinjun Xiong(3), Kaushik Ravindran(2), S.G. Walker(2), S. Narayan(2), L.T. Pillage(2), Ronald A. Rohrer(2), Ibrahim M. Elfadel(2), W. W. Molzen(2), P.R. O'Brien(2), Philip N. Strenski(2)