M. Murakata

Engineering · Physical Sciences

7h-index187citations21works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(11), VLSI and FPGA Design Techniques(10), VLSI and Analog Circuit Testing(7), Semiconductor materials and devices(4), Advancements in Semiconductor Devices and Circuit Design(4)

Publications21 total

An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing
2020· 6 cited
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits
IEICE Transactions on Electronics·2010· 8 cited
Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node
2008· 2 cited
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM
2008· 19 cited
Increasing minimum operating voltage (V<sub>DDmin</sub>) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators
2008· 27 cited
A 63-mW H.264/MPEG-4 Audio/Visual Codec LSI With Module-Wise Dynamic Voltage/Frequency Scaling
IEEE Journal of Solid-State Circuits·2005· 35 cited
An H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling
2005· 20 cited
A parallel global router for sea-of-gates arrays
2003· 1 cited
A DRAM module generator with an expandable cell array scheme
2002· 2 cited
A clock-gating method for low-power LSI design
2002· 27 cited
Concurrent logic and layout design system for high performance LSIs
2002· 7 cited
Fanout-tree restructuring algorithm for post-placement timing optimization
2002· 5 cited
SCR : SPICE Netlist Reduction Tool
1999· 1 cited
SCR : SPICE Netlist Reduction Tool (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences·1999· 1 cited
A Module Generator for Embedded DRAM Macros
Technical report of IEICE. VLD·1997
Layout driven re-synthesis for low power consumption LSIs
1997· 9 cited
Physical design CAD in deep sub-micron era
European Design Automation Conference·1996· 5 cited
Switching activity analysis for sequential circuits using Boolean approximation method
International Symposium on Low Power Electronics and Design·1996· 6 cited
Fanout-tree restructuring algorithm for post-placement timing optimization
1995· 5 cited
Timing Driven Placement By The Path Delay Relaxation Force Method
1992· 1 cited
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Frequent Co-authors

T. Mitsuhashi(8), F. Minami(4), Takahiro Aoki(4), Takeshi Kitahara(3), Taro Niiyama(3), Zhe Yong Piao(3), Koichi Ishida(3), Makoto Takamiya(3), Takayasu Sakurai(3), Masaaki Yamada(3), Hideki Takeuchi(3), T. Fujiyoshi(2), S. Shiratake(2), Shuou Nomura(2), Takafumi Nishikawa(2), Yoshiyuki Kitasho(2), Hideho Arakida(2), Y. Okuda(2), Yoshiyuki Tsuboi(2), Mototsugu Hamada(2)