Ching‐En Lee

Feng Chia University — Taiwan

Engineering · Physical Sciences

11h-index489citations47works0.02yr avg
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Research Topics

Scheduling and Optimization Algorithms(14), Advanced Manufacturing and Logistics Optimization(11), CCD and CMOS Imaging Sensors(9), Assembly Line Balancing Optimization(6), Copper Interconnects and Reliability(5)

Publications47 total

Reinforcement in electromigration reliability of Cu interconnects by alloying of extremely dilute MnO
Journal of Alloys and Compounds·2023
Reinforcement in Electromigration Reliability of Cu Interconnects by Alloying of Extremely Dilute Mno
SSRN Electronic Journal·2023Open Access
Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer
Journal of The Electrochemical Society·2022· 4 cited
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters
IEEE Journal of Solid-State Circuits·2022· 3 cited
All-wet encapsulation and electroless superfilling process for the fabrication of self-assembled-monolayer encapsulated copper interconnects with enhanced electromigration reliability
Materials Letters·2021· 3 cited
Strengthening the Electromigration Resistance of Nanoscaled Copper Lines by (3-aminopropyl)trimethoxysilane Self-Assembled Monolayer
ECS Journal of Solid State Science and Technology·2021· 6 cited
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters
2021· 2 cited
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference
IEEE Journal of Solid-State Circuits·2020· 91 cited
Domain-Specific Computing Architectures and Paradigms
Deep Blue (University of Michigan)·2020
A Pre-Bootstrapping Method for Use in Gate Driver Circuits to Improve the Scan Pulse Delay of High-Resolution TFT-LCD Systems
IEEE Transactions on Industrial Electronics·2019· 10 cited
SNAP: A 1.67 — 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS
2019· 46 cited
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification
IEEE Journal of Solid-State Circuits·2019· 3 cited
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA
2019· 27 cited
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA
arXiv (Cornell University)·2018· 3 citedOpen Access
High-performance spiking neural net accelerators for embedded computer vision applications
2017
New gate driver circuit using pre-charge structure for active-matrix LCDs equipped with in-cell touch structure
International Workshop on Active-Matrix Flatpanel Displays and Devices·2017
A 127mW 1.63TOPS sparse spatio-temporal cognitive SoC for action classification and motion tracking in videos
2017· 5 cited
Ceramide Induced Regulated Alternative Translocation of TM4SF20 and Beyond
The FASEB Journal·2017
Insertion of Simple Structure Between Gate Driver Circuits to Prevent Stress Degradation in In-Cell Touch Panel Using Multi-V Blanking Method
Journal of Display Technology·2016· 8 cited
Inverting the Topology of a Transmembrane Protein by Regulating the Translocation of the First
2016
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Frequent Co-authors

Zhengya Zhang(7), Chih‐Lung Lin(5), Jau-Shiung Fang(5), Yi-Lung Cheng(5), Giin-Shan Chen(5), Chester Liu(4), Yu‐Hsin Lin(4), Fuh‐Der Chou(4), Tzu-Yun Chang(3), Chia‐En Wu(3), Thomas Chen(3), 李慶恩(3), Zhang Jie-Fang(2), Yakun Sophia Shao(2), Stephen W. Keckler(2), Sherry C. Hou(2), Lara L. Hause(2), Kanika Gera(2), Kevin S. McIver(2), Cheng Fu(2)