G. Katopis

IBM (United States) — United States

Engineering · Physical Sciences

17h-index1.5kcitations78works0.02yr avg
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Research Topics

Electromagnetic Compatibility and Noise Suppression(47), 3D IC and TSV technologies(30), Low-power high-performance VLSI design(24), Electrostatic Discharge in Electronics(13), Interconnection Networks and Systems(12)

Publications78 total

A new approach to deriving packaging system statistical eye diagram based on parallel non-linear transient simulations using multiple short signal bit patterns
2012· 10 cited
Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links
IEEE Transactions on Components Packaging and Manufacturing Technology·2011· 6 cited
Application of the Short-Pulse Propagation Technique for Broadband Characterization of PCB and Other Interconnect Technologies
IEEE Transactions on Electromagnetic Compatibility·2010· 22 cited
Time-domain simulation of system interconnect using convolution and Newton-Raphson iteration methods
2010· 5 cited
Searching for the worst-case eye diagram of a signal channel in electronic packaging system including the effects of the nonlinear I/O devices and the crosstalk from adjacent channels
2009· 8 cited
Design methodology of high performance on-chip global interconnect using terminated transmission-line
2009· 13 cited
Desig nMethodolog yo fHig hPerformanc eOn-Chi pGloba lInterconnect Using Terminated Transmission-Line
2009
An analysis on measurement sensitivity of Short-Pulse Propagation technique using a virtual test bench
2008· 2 cited
On-chip bus signaling using passive compensation
2008· 3 cited
Low power passive equalizer optimization using tritonic step response
2008· 8 cited
Low Power Passive Equalizer Design for Computer Memory Links
2008· 10 cited
Predicting and Optimizing Jitter and Eye-Opening Based on Bitonic Step Response
2007· 12 cited
Determination of transmission line parameters in time- and frequency domain for product related packaging structures
2007
Distortion Minimization for Packaging Level Interconnects
2006· 6 cited
Wire and Via Modeling and Simulation Solutions for a Tri-Grid Mesh Plane Ceramic Packaging
2006
High-End Server System Partitioning for Cost Reduction
IEEE Transactions on Advanced Packaging·2006· 1 cited
Comparison of time- and frequency domain measurement results for product related card and MCM transmission lines up to 65 GHz
2006· 6 cited
Feature - From chips to systems via packaging - A comparison of IBM's mainframe servers
IEEE Circuits and Systems Magazine·2006· 3 cited
Decoupling capacitor effects on switching noise
2005· 13 cited
Efficient modeling methodology and hardware validation of glass-ceramic based wiring for high-performance single- and multi-chip modules
2005· 4 cited
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Frequent Co-authors

Dale Becker(23), A. Deutsch(14), G.V. Kopcsay(8), C.W. Surovic(8), H. Smith(7), Chung‐Kuan Cheng(6), H.H. Smith(5), P. Coteus(5), B.J. Rubin(5), Zhaoqing Chen(5), Igor Simone Stievano(5), Flavio Canavero(5), P.J. Restle(4), Rajiv Dunne(4), Tom Gallo(4), Lewis M. Terman(4), G.A. Sai-Halasz(4), D.R. Knebel(4), E. Klink(4), H. Stoller(4)