S. Denorme

STMicroelectronics (France) — France

Engineering · Physical Sciences

16h-index905citations64works0.02yr avg
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Research Topics

Semiconductor materials and devices(55), Advancements in Semiconductor Devices and Circuit Design(50), Integrated Circuits and Semiconductor Failure Analysis(20), Ferroelectric and Negative Capacitance Devices(14), Advanced Memory and Neural Computing(7)

Publications64 total

Improvement of performances HfO 2 -based RRAM from elementary cell to 16 kb demonstrator by introduction of thin layer of Al 2 O 3
Solid-State Electronics·2016· 23 cited
Endurance/Retention Trade Off in HfOx and TaOx Based RRAM
2016· 34 cited
Benefit of Al<inf>2</inf>O<inf>3</inf>/HfO<inf>2</inf> bilayer for BEOL RRAM integration through 16kb memory cut characterization
2015· 13 cited
Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology
2015· 6 cited
28nm advanced CMOS resistive RAM solution as embedded non-volatile memory
2014· 48 cited
Effect of SET temperature on data retention performances of HfO<inf>2</inf>-based RRAM cells
2014· 10 citedOpen Access
ADVANCED SOLUTIONS FOR MOBILITY ENHANCEMENT IN <font>SOI</font> MOSFETS
Frontiers in Electronics·2013
UTBOX and ground plane combined with Al&lt;inf&gt;2&lt;/inf&gt;O&lt;inf&gt;3&lt;/inf&gt; inserted in TiN gate for V&lt;inf&gt;T&lt;/inf&gt; modulation in fully-depleted SOI CMOS transistors
2011· 2 cited
ADVANCED SOLUTIONS FOR MOBILITY ENHANCEMENT IN SOI MOSFETS
International Journal of High Speed Electronics and Systems·2011
A solution for an ideal planar multi-gates process for ultimate CMOS?
2010· 6 cited
Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications
2010· 3 cited
Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below
Solid-State Electronics·2010· 63 cited
Efficient multi-V&lt;inf&gt;T&lt;/inf&gt; FDSOI technology with UTBOX for low power circuit design
2010· 69 cited
New insight on V&lt;inf&gt;T&lt;/inf&gt; stability of HK/MG stacks with scaling in 30nm FDSOI technology
2010· 6 cited
Hybrid Localized SOI/bulk technology for low power system-on-chip
2010· 2 cited
Gate-all-around technology: Taking advantage of ballistic transport?
Solid-State Electronics·2010· 22 cited
Localized SOI logic and bulk I/O devices co-integration for Low power System-on-Chip technology
2010· 3 cited
Thin-film devices for low power applications
Solid-State Electronics·2009· 28 citedOpen Access
First CMOS Integration of Ultra Thin Body and BOX (UTB2) Structures on Bulk Direct Silicon Bonded (DSB)
HAL (Le Centre pour la Communication Scientifique Directe)·2009
Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
2009· 45 cited
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Frequent Co-authors

T. Skotnicki(33), C. Fenouillet-Béranger(25), F. Leverd(24), S. Barnola(23), P. Gouraud(23), P. Perreau(22), F. Bœuf(22), N. Loubet(21), C. Laviron(16), G. Bidal(16), R. Beneyton(13), T. Salvetat(12), Y. Campidelli(12), S. Monfray(12), L. Tosti(11), J.-L. Huguenin(11), O. Faynot(10), C. Borowiak(10), S. Haendler(9), R. Pantel(9)