Linyan Mei

KU Leuven — Belgium

Computer Science · Physical Sciences

12h-index523citations25works6.02yr avg
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Research Topics

Parallel Computing and Optimization Techniques(16), Advanced Neural Network Applications(15), Advanced Memory and Neural Computing(14), CCD and CMOS Imaging Sensors(8), Advanced Data Storage Technologies(6)

Publications25 total

Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators
IEEE Transactions on Computers·2024· 6 citedOpen Access
ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators
2023· 1 citedOpen Access
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
2023· 4 citedOpen Access
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
arXiv (Cornell University)·2023Open Access
PetaOps/W edge-AI $\mu$ Processors: Myth or reality?
2023· 4 citedOpen Access
Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators
2023· 9 cited
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling
2023· 34 cited
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge
IEEE Journal of Solid-State Circuits·2023· 42 cited
TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge
arXiv (Cornell University)·2023· 2 citedOpen Access
Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators
arXiv (Cornell University)·2022· 6 citedOpen Access
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling
arXiv (Cornell University)·2022· 1 citedOpen Access
TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 27 cited
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)·2022· 16 citedOpen Access
Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation
IEEE Transactions on Circuits and Systems I Regular Papers·2022· 16 citedOpen Access
ML Processors Are Going Multi-Core: A performance dream or a scheduling nightmare?
IEEE Solid-State Circuits Magazine·2022· 14 cited
Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing
IEEE Journal on Emerging and Selected Topics in Circuits and Systems·2021· 11 cited
Processor Architecture Optimization for Spatially Dynamic Neural Networks
2021· 7 cited
Survey and Benchmarking of Precision-Scalable MAC Arrays for Embedded DNN Processing.
arXiv (Cornell University)·2021· 1 citedOpen Access
LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation
2021· 20 cited
Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks
2021· 2 cited
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Frequent Co-authors

Marian Verhelst(25), Arne Symons(8), Pouya Houshmand(7), Vikram Jain(7), Juan Sebastian Piedrahita Giraldo(4), Steven Colleman(4), Jaro De Roose(3), Bert Boons(3), Susmita Kar(3), Luca Benini(3), Peter Debacker(2), Koen Goetschalckx(2), Ehab M. Ibrahim(2), Man Shi(2), Victor J. B. Jung(2), Vincent Camus(1), Christian Enz(1), Mohit Dandekar(1), Dimitrios Rodopoulos(1), Jeremy Constantin(1)