P. Nguyen

Leibniz University Hannover — Germany

Engineering · Physical Sciences

9h-index278citations24works1.02yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(15), Semiconductor materials and devices(14), Integrated Circuits and Semiconductor Failure Analysis(5), Geochemistry and Geologic Mapping(3), Silicon Carbide Semiconductor Technologies(2)

Publications24 total

Deep learning-aided inverse design of porous metamaterials
Computer Methods in Applied Mechanics and Engineering·2025· 1 citedOpen Access
Deep learning-aided inverse design of porous metamaterials
arXiv (Cornell University)·2025Open Access
Environment-dependent mutualism–parasitism transitions in the incipient symbiosis between <i>Tetrahymena utriculariae</i> and <i>Micractinium tetrahymenae</i>
The ISME Journal·2025· 2 citedOpen Access
Petrography and trace element signatures of iron-oxides in deposits from the Middleback Ranges, South Australia: From banded iron formation to ore
Ore Geology Reviews·2018· 22 cited
Nonrandom Device Mismatch Considerations in Nanoscale SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2011· 16 cited
A robust 45nm gate-length CMOSFET for 90nm Hi-speed technology
Solid-State Electronics·2006· 1 cited
Interaction of infiltrated colloidal PbS nanocrystals with high Q/V silicon photonic bandgap nanocavities for near-infrared enhanced spontaneous emissions
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2005· 4 cited
Sub-Audio Magnetic Survey Experiments for High-Resolution, Subsurface Mapping of Regolith and Mineralisation at the Songvang Gold Mine near Agnew, Western Australia
Exploration Geophysics·2005· 6 cited
Advanced gate stacks with fully silicided (FUSI) gates and high-k dielectrics. enhanced performance at reduced gate leakage
2005· 28 cited
Sub-audio magnetic survey experiments for high-resolution, subsurface mapping of regolith and mineralisation over a blind gold discovery near Agnew in Western Australia
ASEG Extended Abstracts·2004· 3 citedOpen Access
High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering
2004· 76 cited
Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow
2004· 24 cited
Dual work function metal gate CMOS using CVD metal electrodes
2004· 18 cited
Bandgap Maximization in Photonic Crystals
APS·2003
Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology
2003· 22 cited
A comparative device and performance analysis between a Si-Ge epitaxial-base HBT and a Si double-poly I/I BJT npn structure
2003· 3 cited
Modeling the small-emitter effect in polysilicon-emitter transistors
2003
Low Tinv (≤ 1.8 nm) Metal-Gated MOSFETs on SiO2 Based Gate Dielectrics for High Performance Logic Applications
2003· 3 cited
W/HfO2 gate stacks with Tinv～1.2nm and low charge trapping
2003· 1 cited
Scalability and biasing strategy for CMOS with active well bias
2002· 31 cited
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Frequent Co-authors

C. Wann(7), V. Ku(6), An Steegen(6), P. Jamison(5), Vijay Narayanan(5), R. Rengarajan(4), N. Rovedo(4), Agnese Callegari(4), M. Gribelyuk(4), R.S. Amos(3), D. Lacey(3), C. Cabral(3), H.C. Ng(3), S.E. Fischer(3), V. Chan(2), Ashima Chakravarti(2), Shiwei Yang(2), Shih-Fen Huang(2), T. Schafbauer(2), D. Vietzke(2)