V. Ku

Applied Materials (United States) — United States

Engineering · Physical Sciences

13h-index645citations23works0.02yr avg
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Research Topics

Semiconductor materials and devices(18), Advancements in Semiconductor Devices and Circuit Design(16), Integrated Circuits and Semiconductor Failure Analysis(6), Plasma Diagnostics and Applications(5), Dust and Plasma Wave Phenomena(4)

Publications23 total

Investigation of VT Shift Mechanism of High-K Dielectrics caused by Lanthanum Capping for NMOS and Tantalum Capping for PMOS Devices
ECS Transactions·2008· 3 cited
Enabling Effective Work Function Tuning by RF-PVD Metal Oxide on High-k Gate Dielectric
ECS Transactions·2008· 2 cited
Enabling Effective Work Function Tuning by RFPVD Metal Oxide on High-k Gate Dielectric
ECS Meeting Abstracts·2008
High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates
2006· 15 cited
65nm cmos technology for low power applications
2006· 44 cited
Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS
2006· 5 cited
Direct Silicon Bonded (DSB) Mixed Orientation Substrate for High Performance Bulk CMOS Technology
2006
Resonances In A Radio-frequency Plasma
2005
High performance and low power transistors integrated in 65nm bulk CMOS technology
2005· 81 cited
Advanced gate stacks with fully silicided (FUSI) gates and high-k dielectrics. enhanced performance at reduced gate leakage
2005· 28 cited
High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering
2004· 76 cited
Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow
2004· 24 cited
Dual work function metal gate CMOS using CVD metal electrodes
2004· 18 cited
Two gates are better than one [double-gate MOSFET process]
IEEE Circuits and Devices Magazine·2003· 81 cited
Low Tinv (≤ 1.8 nm) Metal-Gated MOSFETs on SiO2 Based Gate Dielectrics for High Performance Logic Applications
2003· 3 cited
W/HfO2 gate stacks with Tinv～1.2nm and low charge trapping
2003· 1 cited
Device design considerations for ultra-thin SOI MOSFETs
2003· 55 cited
Triple-self-aligned, planar double-gate MOSFETs: devices and circuits
2002· 68 cited
Novel process integration for reduction of subquarter-micron contact resistance
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena·1999
Study of the SiO2-to-Si3N4 etch selectivity mechanism in the presence of polymers in fluorocarbon plasmas
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena·1999· 5 cited
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Frequent Co-authors

An Steegen(8), C. Wann(6), P. Nguyen(6), Vijay Narayanan(6), P. Jamison(6), C. Cabral(5), P. Kozlowski(4), V. Chan(4), R. Rengarajan(4), N. Rovedo(4), B. M. Annaratone(4), J. E. Allen(4), Agnese Callegari(4), M. Gribelyuk(4), D. Boyd(3), J. Newbury(3), Christopher Baiocco(3), F. Jamin(3), R. Mo(3), M. Ieong(3)