Hidetoshi Onodera

Sanyo-Onoda City University — Japan

Engineering · Physical Sciences

31h-index4.9kcitations621works3.02yr avg
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Research Topics

Low-power high-performance VLSI design(174), Advancements in Semiconductor Devices and Circuit Design(119), VLSI and Analog Circuit Testing(113), Semiconductor materials and devices(109), Rare-earth and actinide compounds(69)

Publications620 total

Quantitation of Vaporized γ‐Aminobutyric Acid in Cigarette Smoke Extract From e‐Cigarettes by the Combination of HPLC‐Fluorescence Detection and Derivatization With DBD‐F
Luminescence·2024· 3 citedOpen Access
Measuring method of loss for optical waveguides by use of a rectangular glass probe
Kyoto University Research Information Repository (Kyoto University)·2023
Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences·2022· 1 citedOpen Access
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits
2022
Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation
Japanese Journal of Applied Physics·2022· 1 citedOpen Access
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2022· 10 cited
Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization
2022
Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region
2022· 1 cited
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
2021· 1 cited
CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models
2021· 3 cited
Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences·2021
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences·2021· 1 cited
Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences·2021· 1 cited
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation
IEICE Transactions on Electronics·2021
Supplemental PDK for ASAP7 Using Synopsys Flow
IPSJ Transactions on System and LSI Design Methodology·2021· 3 citedOpen Access
Monitor Circuits for Cross-Layer Resiliency
Embedded systems·2020· 1 citedOpen Access
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias
2020· 3 cited
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics
2020
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching
IEEE Open Journal of Circuits and Systems·2020· 1 citedOpen Access
MCell
2020· 9 cited
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Frequent Co-authors

Kazutoshi Kobayashi(9), Masanori Hashimoto(7), T. Ohnishi(4), Jun Furuta(4), Mahfuzul Islam(4), Takashi Matsumoto(4), K. Hono(3), Keikichi Tamaru(3), A. Shibatomi(3), S. Shimomura(3), Kenichi Okada(3), Shinichi Nishizawa(3), M. Ohnuma(2), H. Fujimori(2), K. Tamaru(2), N. Yokoyama(2), Chika Hayashi(2), Masaichiro Mizumaki(2), Naoki Yokoyama(2), H. Yamauchi(2)