Christian Menolfi

IBM Research - Zurich — Switzerland

Engineering · Physical Sciences

33h-index3.6kcitations111works0.02yr avg
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Research Topics

Advancements in PLL and VCO Technologies(60), Radio Frequency Integrated Circuit Design(39), Analog and Mixed-Signal Circuit Design(34), Photonic and Optical Devices(26), Semiconductor Lasers and Optical Devices(16)

Publications111 total

A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)·2022· 10 citedOpen Access
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET
2019· 10 citedOpen Access
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
IEEE Journal of Solid-State Circuits·2019· 57 citedOpen Access
30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
2019· 18 citedOpen Access
6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
2019· 66 cited
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET
IEEE Journal of Solid-State Circuits·2018· 31 cited
A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
IEEE Journal of Solid-State Circuits·2018· 83 cited
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
2018· 6 cited
A 10-Bit 20–40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
2018· 26 cited
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
2018· 8 cited
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
IEEE Transactions on Circuits and Systems I Regular Papers·2018· 19 citedOpen Access
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET
IEEE Journal of Solid-State Circuits·2018· 19 citedOpen Access
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET
2018· 38 citedOpen Access
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS
2018· 25 citedOpen Access
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
2018· 79 citedOpen Access
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels
IEEE Journal of Solid-State Circuits·2018· 42 citedOpen Access
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
2018· 3 citedOpen Access
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
IEEE Conference Proceedings·2018
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
IEEE Journal of Solid-State Circuits·2017· 86 citedOpen Access
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET
2017· 5 cited
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Frequent Co-authors

Thomas Toifl(43), Thomas Morf(37), Marcel Kossel(36), Pier Andrea Francese(29), Lukas Kull(27), Martin Schmatz(17), Matthias Brändli(16), P. Buchmann(16), Matthias Bräendli(15), Toke Meyer Andersen(13), Danny Luu(13), Alessandro Cevrero(12), İlter Özkaya(12), Yusuf Leblebici(10), Jonas Weiß(6), Marcel Kossel(6), Thomas Morf(5), Qiuting Huang(5), Florian Krismer(5), Johann W. Kolar(5)