A. Mercha

IMEC — Belgium

Engineering · Physical Sciences

38h-index5.1kcitations257works0.02yr avg
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Research Topics

Semiconductor materials and devices(196), Advancements in Semiconductor Devices and Circuit Design(185), Integrated Circuits and Semiconductor Failure Analysis(73), Radio Frequency Integrated Circuit Design(55), Ferroelectric and Negative Capacitance Devices(29)

Publications257 total

Channel Length Dependence of PBTI in High-k First RMG Gate Stack Integration Scheme
2021
Plasma Charging Damage in HK-First and HK-Last RMG NMOS Devices
IEEE Transactions on Device and Materials Reliability·2021· 4 cited
Cumulated charging mechanisms at gate processing in high-κ first planar NMOS devices
2020· 1 cited
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2017· 54 cited
Impact of Wire Geometry on Interconnect <italic>RC</italic> and Circuit Delay
IEEE Transactions on Electron Devices·2016· 125 cited
Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2016· 25 cited
Architectural strategies in standard-cell design for the 7 nm and beyond technology node
Journal of Micro/Nanolithography MEMS and MOEMS·2016· 19 cited
A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs
IEEE Transactions on Electron Devices·2015· 35 cited
Self-heating on bulk FinFET from 14nm down to 7nm node
2015· 92 cited
A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS
2015
Holisitic device exploration for 7nm node
2015· 43 cited
Impact of device and interconnect process variability on clock distribution
2015· 2 cited
Vertical device architecture for 5nm and beyond: Device & circuit implications
2015· 49 cited
Impact of fin shape variability on device performance towards 10nm node
2015· 8 cited
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
2015· 12 cited
Modeling FinFET metal gate stack resistance for 14nm node and beyond
2015· 6 cited
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
2015· 48 cited
Lateral NWFET optimization for beyond 7nm nodes
2015· 14 cited
Variability of quadruple-patterning interconnect processes
2015· 8 cited
Maintaining Moore’s law: enabling cost-friendly dimensional scaling
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2015· 33 cited
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Frequent Co-authors

Bertrand Parvais(14), Nadine Collaert(13), Diederik Verkest(11), Stefaan Decoutere(10), M. Dehan(9), Aaron Thean(9), Piet Wambacq(9), M. Jurczak(9), Eddy Simoen(8), Eric Beyne(7), G. Groeseneken(7), S. Biesemans(7), Julien Ryckaert(7), Geert Van der Plas(6), Dmitry Yakimets(6), Trong Huynh-Bao(6), V. Subramanian(6), Ingrid De Wolf(5), J. Van Olmen(5), Michał Rakowski(5)