Dmitry Yakimets

Vienna Consulting Engineers (Austria) — Austria

Engineering · Physical Sciences

24h-index1.9kcitations51works2.62yr avg
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Research Topics

Semiconductor materials and devices(44), Advancements in Semiconductor Devices and Circuit Design(42), Ferroelectric and Negative Capacitance Devices(20), Nanowire Synthesis and Applications(12), Integrated Circuits and Semiconductor Failure Analysis(8)

Publications51 total

Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height
IEEE Journal of the Electron Devices Society·2024· 2 citedOpen Access
Design Decoupling of Inner- and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling
IEEE Journal of the Electron Devices Society·2024· 2 citedOpen Access
Comprehensive DTCO-Driven Power and Performance Optimization in Nanosheet and Forksheet Architectures: Influence of Dielectric Walls, Active Widths, and Power Delivery Methods
2024Open Access
Inflection Points in Cfet Scaling: Impact of Dtco Boosters
2024
DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance
2024· 5 cited
Scaling Options for GAA Nanosheet Based Devices: Role of Decoupling Inner- and Outer-Gate Lengths
2024· 1 cited
Inflection Points in GAA NS-FET to C-FET Scaling Considering Impact of DTCO Boosters
IEEE Transactions on Electron Devices·2024· 8 cited
Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling
IEEE Transactions on Electron Devices·2020· 36 cited
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
2020· 16 cited
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
2019· 107 cited
Ge Devices: A Potential Candidate for Sub-5-nm Nodes?
IEEE Transactions on Electron Devices·2019· 13 cited
Device-, Circuit- & Block-level evaluation of CFET in a 4 track library
2019· 66 cited
Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs
IEEE Transactions on Electron Devices·2019· 4 citedOpen Access
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
2018· 62 cited
Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET
2018Open Access
Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI
IEEE Transactions on Nanotechnology·2018· 131 citedOpen Access
Junctionless versus inversion-mode lateral semiconductor nanowire transistors
Journal of Physics Condensed Matter·2018· 38 cited
Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells
2018· 53 cited
Built-In Sheet Charge As an Alternative to Dopant Pockets in Tunnel Field-Effect Transistors`
IEEE Journal of the Electron Devices Society·2018· 4 citedOpen Access
Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration
2017· 124 cited
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Frequent Co-authors

P. Schuddinck(21), M. Garcia Bardon(20), Nadine Collaert(19), Doyoung Jang(18), Diederik Verkest(18), Trong Huynh-Bao(15), Aaron Thean(15), Geert Eneman(14), A. Mocuta(14), A. Veloso(13), A. Mercha(11), Julien Ryckaert(11), A. Spessot(10), Prasanth Raghavan(10), D. Mocuta(9), Bertrand Parvais(9), Rogier Baert(8), Philippe Matagne(8), Clément Merckling(8), Niamh Waldron(8)