Kenichi Ohhata

Kagoshima University — Japan

Engineering · Physical Sciences

17h-index716citations87works0.02yr avg
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Research Topics

Photonic and Optical Devices(30), Analog and Mixed-Signal Circuit Design(29), Advancements in PLL and VCO Technologies(24), Low-power high-performance VLSI design(22), Semiconductor Lasers and Optical Devices(22)

Publications87 total

High-Precision Open-Loop Time Amplifier Using Current Regulator
2023
A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging
2022· 1 cited
A PVT-Robust Closed-Loop Dynamic Amplifier Using Three-Stage Floating Inverter Amplifier
2021· 1 cited
Stochastic Subranging ADC Using Variable Comparator Offset Technique
2020· 4 cited
A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC
IEEE Journal of Solid-State Circuits·2019· 53 cited
Low-Power, High-Speed Time-Based Subranging ADCs
2018· 1 cited
A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTC
2018· 14 cited
A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2018· 17 cited
900-MHz, 3.5-mW, 8-bit pipelined subranging ADC combining flash ADC and TDC
2017· 7 cited
A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer
Circuits and Systems·2017· 2 citedOpen Access
C-12-29 Design of 500-MS/s, 8-bit, Two-Step Single Slope ADC
Proceedings of the Society Conference of IEICE·2015
C-12-33 Performance comparison of low-voltage comparators
Proceedings of the Society Conference of IEICE·2015
High-speed, low-power subranging ADCs
2015· 2 cited
A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator
Circuits and Systems·2015· 1 citedOpen Access
Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization
2014
Automatic technique of distortion compensation in resistor ladder for high-speed and low-power ADC
IEICE Electronics Express·2014Open Access
A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration
Circuits and Systems·2014· 1 citedOpen Access
1-GHz, 17.5-mW, 8-bit Subranging ADC Using Offset-Cancelling Charge-Steering Amplifier
IEICE Transactions on Electronics·2014· 2 cited
A 20 Gbps inductorless CMOS optical receiver for short-distance VCSEL-based 850 nm optical links
Analog Integrated Circuits and Signal Processing·2013· 5 cited
A 6.5-μV/°C Offset Drift Compensation Technique for Dynamic Comparator
International Journal of Electronics and Electrical Engineering·2013
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Frequent Co-authors

Takatsugu Masuda(11), Katsuyoshi Washio(11), H. Nambu(11), K. Kanetani(11), Kizashi Yamaguchi(11), N. Homma(11), Kiichi Yamashita(9), Y. Idei(8), Nobuhiro Shiramizu(7), K. Higeta(7), E. Ohue(6), Norio Chujo(6), Takahide Ikeda(6), T. Kusunoki(6), M. Usami(6), Takashi Harada(5), H. Shimamoto(5), F. Arakawa(5), Katsuyoshi Harasawa(4), Osamu Hirota(4)