K. Kanetani

Hitachi (Japan) — Japan

Engineering · Physical Sciences

9h-index252citations32works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(24), Semiconductor materials and devices(15), Advancements in Semiconductor Devices and Circuit Design(10), VLSI and Analog Circuit Testing(8), Radiation Effects in Electronics(6)

Publications32 total

A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram
2005· 8 cited
Development of environmentally friendly energy-efficient copier
Proceedings Second International Symposium on Environmentally Conscious Design and Inverse Manufacturing·2003· 2 cited
Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core
2003· 7 cited
A 550-ps access, 900-MHz, 1-Mb ECL-CMOS SRAM
2003· 5 cited
An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM
2003· 10 cited
Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time
2003· 7 cited
A redundancy technique for ultra-high-speed SRAMs
2002
A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM
2002· 20 cited
A novel BiCMOS circuit using a base boost technique for low voltage application
2002
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM
IEEE Journal of Solid-State Circuits·2000· 7 cited
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz
IEEE Journal of Solid-State Circuits·2000· 2 cited
High-speed SRAM Circuit Technology「A 1.8ns Access, 550MHz 4.5Mb CMOS SRAM」「Synonym Hit RAM: A 500MHz 1.5ns CMOS SRAM Macro with 576b Parallel Comparison and Parity Check Functions」
Technical report of IEICE. ICD·1998· 1 cited
Design of a 2 - ns Cycle Time 72 - kb ECL - CMOS SRAM Macro
IEICE Transactions on Electronics·1998· 2 cited
A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM
IEEE Journal of Solid-State Circuits·1998· 65 cited
A BiCMOS Circuit Using a Base-Boost Technique for Low-Voltage, Low-Power Application
IEICE Transactions on Electronics·1996· 2 cited
Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOS SRAM
IEICE Transactions on Electronics·1996
A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM(Special Issue on the 1994 VLSI Circuits Symposium)
IEICE Transactions on Electronics·1995
A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM
IEICE Transactions on Electronics·1995
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM
IEEE Journal of Solid-State Circuits·1995· 16 cited
Noise Reduction Techniques for a 64kb ECL-CMOS SRAM with a 2ns Cycle Time (Special Issue on LSI Memories)
IEICE Transactions on Electronics·1993
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Frequent Co-authors

N. Homma(28), H. Nambu(24), Kenichi Ohhata(22), Kizashi Yamaguchi(16), T. Kusunoki(14), Y. Idei(13), K. Higeta(12), Takahide Ikeda(12), Kunihiko Yamaguchi(10), N. Tamba(8), K. Yamasaki(6), M. Usami(6), K. Ogiue(6), Toshiro Hiramoto(5), M. Odaka(5), Y. Sakurai(5), M. Ohayashi(5), Kazuki Watanabe(4), H. Nanbu(4), A. Uchida(4)