K. Ogiue

Hitachi (Japan) — Japan

Engineering · Physical Sciences

14h-index519citations36works0.02yr avg
OpenAlex↗Google Scholar↗Lab page↗

Accepting Students?

No reports yet. Know if this professor is taking students?

Research Topics

Low-power high-performance VLSI design(22), Semiconductor materials and devices(20), Advancements in Semiconductor Devices and Circuit Design(14), Parallel Computing and Optimization Techniques(13), Analog and Mixed-Signal Circuit Design(6)

Publications36 total

A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array
2003· 11 cited
A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array
2003· 25 cited
An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM
2003· 10 cited
An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM
IEEE Journal of Solid-State Circuits·1989· 12 cited
An 8 ns 256 K BiCMOS RAM
IEEE Journal of Solid-State Circuits·1989· 16 cited
SESSION 2: HIGH-SPEED SRAMs WAM 2.2: A 512kb/5ns BiCMOS RAM with 1 kG/150ps Logic Gate Array
1989
Perspective on BiCMOS VLSIs
IEEE Journal of Solid-State Circuits·1988· 68 cited
IEEE 1988 Bipolar Circuits E Tdnology Meeting 'An Experimental Soft-error Immune 64-Kb 3ns ECL Bipolar RAM"
1988· 2 cited
3.8ns operation cycle RAM-with-logic LSI
1988
A 7-ns/350-mW 64-kbit ECL-compatible RAM
IEEE Journal of Solid-State Circuits·1987· 15 cited
High Performance Bi-CMOS Technology and its Applications
1987· 1 cited
Ultra-thin Ta<sub>2</sub>O<sub>5</sub>dielectric film for high-speed bipolar memories
IEEE Transactions on Electron Devices·1987· 57 cited
High-speed BiCMOS technology with a buried twin well structure
IEEE Transactions on Electron Devices·1987· 51 cited
A 7ns/350mW 64K ECL compatible RAM
1987· 19 cited
4–kbit bipolar RAM with on–chip address latch function
Electronics and Communications in Japan (Part II Electronics)·1987· 1 cited
A 7ns 128K multichip ECL RAM-withLogic module
1987· 1 cited
A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM
IEEE Journal of Solid-State Circuits·1986· 16 cited
13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology
IEEE Journal of Solid-State Circuits·1986· 33 cited
A 13ns/350mW 2Kw × 9b RAM using Hi-BiCMOS Technology
1986
A 3.5ns, 2W, 20mm<sup>2</sup>16Kb ECL bipolar RAM
1986· 9 cited
page 1 of 2Next →

Frequent Co-authors

Takahide Ikeda(12), M. Odaka(12), A. Uchida(10), N. Homma(9), Kizashi Yamaguchi(7), S. Miyaoka(6), Hiroyoshi Higuchi(6), K. Kanetani(6), I. Masuda(4), M. Hirao(4), H. Nanbu(4), Yasushiro Nishioka(3), N. Tamba(3), K. Tonomura(3), Makoto Suzuki(3), Tohru Nakamura(3), M. Iwabuchi(3), K. Akimoto(3), Hiroaki Miwa(3), Masanori Odaka(3)