N. Tamba

Engineering · Physical Sciences

9h-index253citations27works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(15), Semiconductor materials and devices(13), Advancements in Semiconductor Devices and Circuit Design(8), Parallel Computing and Optimization Techniques(4), Analog and Mixed-Signal Circuit Design(4)

Publications27 total

A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences·2020· 3 cited
A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System
2019· 3 cited
Prototyping of Real-time Computer-Aided Diagnosis System for Colorectal Endoscopic Movies and Images with Machine Learning
IEICE Technical Report; IEICE Tech. Rep.·2018
Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM
2018· 9 cited
A closed-form analysis of f/sub T/ for the bipolar transistor down to liquid nitrogen temperature
2003· 2 cited
Hot-electron-induced minority carrier generation in bipolar junction transistors
2003· 4 cited
Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time
2003· 7 cited
A redundancy technique for ultra-high-speed SRAMs
2002
A 0.35 μm ECL-CMOS process technology on SOI for 1 ns mega-bits SRAMs with 40 ps gate array
2002· 7 cited
A 450 MHz 64 b RISC processor using multiple threshold voltage CMOS
2002· 21 cited
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%
2002· 1 cited
A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation
2002· 3 cited
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%
IEEE Journal of Solid-State Circuits·2001· 6 cited
A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation
Technical report of IEICE. ICD·2000· 5 cited
A Bipolar-Based 0.5μm BiCMOS Technology on Bonded SOI for High-Speed LSIs (Special Section on High Speed and High Density Multi Functional LSI Memories)
IEICE Transactions on Electronics·1994· 1 cited
A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates
IEEE Journal of Solid-State Circuits·1994· 4 cited
Noise Reduction Techniques for a 64kb ECL-CMOS SRAM with a 2ns Cycle Time (Special Issue on LSI Memories)
IEICE Transactions on Electronics·1993
Redundancy Technique for Ultra-High-Speed Static RAMs
IEICE Transactions on Electronics·1993
A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates
1993· 16 cited
High-speed sensing techniques for ultrahigh-speed SRAMs
IEEE Journal of Solid-State Circuits·1992· 16 cited
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Frequent Co-authors

Takahide Ikeda(15), M. Odaka(10), H. Nambu(10), K. Kanetani(8), Y. Idei(8), Kizashi Yamaguchi(8), N. Homma(8), Toshiro Hiramoto(8), Kenichi Ohhata(8), Kazuki Watanabe(7), Y. Sakurai(5), Tetsushi Koide(4), Hiroshi Mieno(4), Hiroshi Toishi(4), Takayuki Sugawara(4), Masayuki Tsuji(4), Masayuki Odagawa(4), Toru Tamaki(4), Bisser Raytchev(4), Kazufumi Kaneda(4)