R. Coquand

Commissariat à l'Énergie Atomique et aux Énergies Alternatives — France

Engineering · Physical Sciences

17h-index1.1kcitations60works0.32yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(46), Semiconductor materials and devices(43), Nanowire Synthesis and Applications(22), Integrated Circuits and Semiconductor Failure Analysis(10), Quantum and electron transport phenomena(5)

Publications60 total

Correction: Understanding nanostructures formation on Si surfaces at the melting threshold by laser annealing
MRS Advances·2025Open Access
Understanding nanostructures formation on Si surfaces at the melting threshold by laser annealing
MRS Advances·2025
Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices
ECS Meeting Abstracts·2024
Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices
ECS Transactions·2024· 2 cited
Silicon nitride photonics: large scale integration and applications
2024
Impact of process parameters on grayscale MEEF
2024
Mask errors impact on grayscale lithography patterning
2023· 1 cited
Microstructure Evolution of Nanosecond Laser Annealed Si/Si<sub>1-X</sub>Ge<sub>x</sub>/Si Structures
ECS Meeting Abstracts·2022
Imaging, Modeling and Engineering of Strain in Gate-All-Around Nanosheet Transitors
2019· 25 cited
Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies
Semiconductor Science and Technology·2019· 21 cited
Ultra Wide Micro Bumps Interconnection Matrix for High Energy Particle Detection: Process and Assembly
2019
Grayscale lithography process study for sub 5µm microlens patterns
2019· 4 citedOpen Access
Stress and Strain Evolution in Stacked Gate-All-Around Transistors for Sub-7nm Node Studied By Advanced Transmission Electron Microscopy Techniques and Finite Element Method Modelling
ECS Meeting Abstracts·2018
Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology
Applied Physics Letters·2018· 39 cited
OxRAM integration above FDSOI transistor drain: Integration approach and process impact on electrical characteristics
Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials·2017
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
2016· 108 citedOpen Access
NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs
2016· 19 citedOpen Access
(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI
ECS Meeting Abstracts·2016
(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI
ECS Transactions·2016· 2 cited
An analysis of stress evolution in stacked GAA transistors
2016· 5 cited
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Frequent Co-authors

Sylvain Barraud(35), T. Poiroux(17), G. Ghibaudo(15), O. Faynot(14), C. Vizioz(14), P. Perreau(13), M. Cassé(12), S. Monfray(11), V. Maffini-Alvaro(10), M. Vinet(10), L. Tosti(10), Masahiro Koyama(9), Marie-Pierre Samson(9), C. Tabone(9), C. Comboroure(8), B. De Salvo(8), S. Reboh(7), E. Augendre(7), F. Bœuf(7), G. Reimbold(7)